Technical Programme Committee 2018

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Topic: D10 Temperature and Variability-Aware System Design and Optimization

Methods, techniques, and architectures for counteracting circuit and system variability due to manufacturing process, temperature, or aging effects, including: design-time and runtime temperature, variability, and reliability management of SoCs and multi-core platforms (both at HW and SW level); modeling and optimization approaches for manufacturing-induced or temperature variations; modeling and optimization methods targeting degradation mechanisms in emerging integration and manufacturing technologies (e.g., 3D stacking).

Chair: Giovanni Ansaloni, USI - Lugano, CH, Contact

Co-Chair: Jose L. Ayala, Complutense University of Madrid, ES, Contact

Members:

  • Georgios Karakonstantis, Queen's University, GB, Contact
  • Mohamed M. Sabry, Stanford University, US, Contact
  • Vasilis Pavlidis, University of Manchester, GB, Contact
  • Qinru Qiu, Syracuse University, US, Contact
  • Rene van Leuken, TU Delft, NL, Contact
  • Pieter Weckx, IMEC, BE, Contact