Technical Programme Committee 2019

Printer-friendly version PDF version

TPC chairs and members can update their personnel data like affiliation in SoftConf only. Please update your data in your SoftConf Profile. This page is updated automatically each full hour.

Track D: Design Methods and Tools (click to open)

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Franco Fummi, Università di Verona, IT, Contact

Topics

D1 System Specification and Modeling (click to open)

Chair: Ingo Sander, KTH Royal Institute of Technology, SE, Contact

Co-Chair: Frederic Mallet, Univ. Nice Sophia Antipolis, FR, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Patricia Derler, National Instruments, US, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Abdoulaye Gamatie, LIRMM / CNRS / UM2, FR, Contact
  • Michael Huebner, Ruhr-University Bochum, DE, Contact
  • Matthias Jung, University of Kaiserslautern, DE, Contact
  • Frederic Mallet, Univ. Nice Sophia Antipolis, FR, Contact
  • Julio Medina, niversidad de Cantabria, ES, Contact
  • Gianluca Palermo, Politecnico di Milano, IT, Contact
  • Martin Radetzki, University of Stuttgart, DE, Contact
  • Ingo Sander, KTH Royal Institute of Technology, SE, Contact

Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; performance modeling; timing analysis; predictive and learning-based models; system-level platform and architecture models and simulation ; heterogeneous systems and models.

D2 System Design, High-Level Synthesis, and Optimization (click to open)

Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact

Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Jason Anderson, University of Toronto, CA, Contact
  • Jason Anderson, University of Toronto, CA, Contact
  • Lars Bauer, Karlsruhe Institute of Technology, DE, Contact
  • Benjamin Carrion Schafer, University of Texas at Dallas, US, Contact
  • Kiyoung Choi, Seoul National University, KR, Contact
  • Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Michael Glaß, Universität Ulm, DE, Contact
  • Soonhoi Ha, Seoul National University, KR, Contact
  • Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact
  • Dirk Koch, University of Manchester, GB, Contact
  • Luciano Lavagno, Politecnico di Torino, IT, Contact
  • David Novo, French National Centre for Scientific Research (CNRS), FR, Contact
  • Sudeep Pasricha, Colorado State University, US, Contact
  • Christian Pilato, Politecnico di Milano, IT, Contact
  • Donatella Sciuto, Politecnico di Milano, IT, Contact
  • jason xue, City University of Hong Kong, HK, Contact
  • Daniel Ziener, University of Twente, NL, Contact

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; multi-objective optimization techniques (e.g., performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.

D3 System Simulation and Validation (click to open)

Chair: Graziano Pravadelli, University of Verona, IT, Contact

Co-Chair: Avi Ziv, IBM Research - Haifa, IL, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Anupam Chattopadhyay, Nanyang Technological University, SG, Contact
  • Flavio M. de Paula, IBM Corporation, US, Contact
  • Monica Farkash, University of Texas at Austin, US, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Daniel Grosse, University of Bremen/DFKI, DE, Contact
  • William Hung, Synopsys Inc., US, Contact
  • Tushar Krishna, Georgia Institute of Technology, US, Contact
  • Katell Morin-Allory, TIMA Laboratory, FR, Contact
  • Graziano Pravadelli, University of Verona, IT, Contact
  • Jaan Raik, Tallinn university of Technology, EE, Contact
  • Sandip Ray, NXP Semiconductors, US, Contact
  • Shobha Vasudevan, UIUC, US, Contact
  • Sara Vinco, Politecnico di Torino, IT, Contact
  • Li-C. Wang, UCSB, US, Contact
  • Avi Ziv, IBM Research - Haifa, IL, Contact

Simulation-based and semi-formal validation and verification of: SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including digital, analog, interconnect and mixed-signal components. In addition: testbench and assertion generation and qualification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon diagnosis and debugging solutions, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities; with or without the employment of artificial intelligence or machine learning techniques.

D4 Formal Methods and Verification (click to open)

Chair: Armin Biere, Johannes Kepler University Linz, AT, Contact

Co-Chair: Alessandro Cimatti, Fondazione Bruno Kessler, IT, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Armin Biere, Johannes Kepler University Linz, AT, Contact
  • Gianpiero Cabodi, Politecnico di Torino, IT, Contact
  • Alessandro Cimatti, Fondazione Bruno Kessler, IT, Contact
  • Koen Claessen, Chalmers University of Technology, SE, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Barbara Jobstmann, EPFL / Cadence, CH, Contact
  • Daniel Kroening, University of Oxford, GB, Contact
  • Alexander Nadel, Intel, IL, Contact
  • Anna Slobodova, Centaur Technology, US, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, decomposition techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

Chair: Georges Gielen, KU Leuven, BE, Contact

Co-Chair: Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Manuel Barragan, TIMA Laboratory, FR, Contact
  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Günhan Dündar, Boğaziçi University, TR, Contact
  • Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Georges Gielen, KU Leuven, BE, Contact
  • Helmut Gräb, Technische Universität München, DE, Contact
  • Deukhyoun Heo, Washington State University, US, Contact
  • Deukhyoun Heo, Washington State University, US, Contact
  • Nuno Horta, Instituto de Telecomunicações /Instituto Superior Técnico – Universidade de Lisboa, PT, Contact
  • Mark Po-Hung Lin, National Chung Cheng University, TW, Contact
  • Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR, Contact
  • Manoj Sachdev, University of Waterloo, CA, Contact
  • Gerd Vandersteen, Vrije Universiteit Brussel - dept. ELEC, BE, Contact

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT6 Design and Test of Secure Systems (click to open)

Chair: Ilia Polian, University of Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Aydin Aysu, University of Texas at Austin, US, Contact
  • Valentina Banciu, Riscure, NL, Contact
  • Lejla Batina, Radboud University Nijmegen, NL, Contact
  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Jean Luc Danger, Télécom ParisTech, FR, Contact
  • Wieland Fischer, Infineon Technologies, DE, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US, Contact
  • Mike Hutter, Cryptography Research Inc., US, Contact
  • Bilge Kavun Elif, Infineon, Ge, Contact
  • Farinaz Koushanfar, University of California San Diego, US, Contact
  • Roel Maes, Intrinsic-ID, NL, Contact
  • Yiorgos Makris, The University of Texas at Dallas, US, Contact
  • Nele Mentens, KU Leuven, BE, Contact
  • David Oswald, School of Computer Science, University of Birmingham, GB, Contact
  • Ilia Polian, University of Stuttgart, DE, Contact
  • Francesco Regazzoni, ALaRI, CH, Contact
  • Kazuo Sakiyama, The University of Electro-Communications, JP, Contact
  • Matthias Sauer, University of Freiburg, DE, Contact
  • Johanna Sepulveda, TU Munich, DE, Contact

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; machine learning for hardware security evaluation .

D7 Network on Chip (click to open)

Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact

Co-Chair: Masoud Daneshtalab, KTH Royal Institute of Technology, SE, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Daniel Chillet, INRIA, FR, Contact
  • Masoud Daneshtalab, KTH Royal Institute of Technology, SE, Contact
  • Masoumeh Ebrahimi, university of Turku, FI, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Bertrand Granado, Sorbonne Université, FR, Contact
  • Ajay Joshi, Boston University, US, Contact
  • Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
  • Romain Lemaire, CEA-Leti, FR, Contact
  • Fernando Moraes, PUCRS University, BR, Contact
  • Gabriela Nicolescu, Ecole Polytechnique de Montréal, CA, Contact
  • Li-Shiuan Peh, Professor, National University of Singapore, SG, Contact
  • Jiang Xu, Hong Kong University of Science and Technology, HK, Contact
  • Davide Zoni, Politecnico di Milano, IT, Contact

Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, NoC and communication-centric design, including: topology, switching, routing and flow control; communication-aware frameworks for Quality-of-Service, security, robustness, power, variability and thermal management; design space exploration frameworks and programming models for communication-centric design; interconnects for domain-specific applications (high performance computing, approximate computing, machine learning, 5G, etc.); design of interconnects using alternative/emerging technologies (photonics/optics, wireless, 3D stacking etc.)

D8 Architectural and Microarchitectural Design (click to open)

Chair: Francisco Cazorla, Barcelona Supercomputing Center and IIIA-CSIC, ES, Contact

Co-Chair: Olivier Sentieys, INRIA, FR, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Jung Ho Ahn, Seoul National University, KR, Contact
  • Mladen Berekovic, TU Braunschweig, DE, Contact
  • Jeronimo Castrillon, TU Dresden, DE, Contact
  • Francisco Cazorla, Barcelona Supercomputing Center and IIIA-CSIC, ES, Contact
  • Jean-Philippe Diguet, Lab-STICC, FR, Contact
  • Zhenman Fang, UCLA/Xilinx, US, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Christophe Jego, Bordeaux INP, CNRS IMS, UMR 5218, FR, Contact
  • Lei Ju, Shandong University, CN, Contact
  • Myoungsoo Jung, Yonsei University, KR, Contact
  • Georgios Keramidas, Think Silicon S.A./Technological Educational Institute of Western Greece, GR, Contact
  • Leonidas Kosmidis, Barcelona Supercomputing Center (BSC-CNS) and Universitat Politècnica de Catalunya, ES, Contact
  • Andrea Marongiu, University of Bologna, IT, Contact
  • Gokhan Memik, Northwestern University, US, Contact
  • Laura Pozzi, USI Lugano, CH, Contact
  • Toshinori Sato, Fukuoka University, JP, Contact
  • Olivier Sentieys, INRIA, FR, Contact
  • Cristina Silvano, Politecnico di Milano, IT, Contact
  • Magnus Själander, Norwegian University of Science and Technology, NO, Contact
  • Lavanya Subramanian, Intel Labs, US, Contact
  • Sotirios Xydis, National Technical University of Athens, GR, Contact

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, safety, and timing predictability.

D9 Power Modeling, Low-Power Design, and Power-Aware Optimization (click to open)

Chair: Naehyuck Chang, KAIST, KR, Contact

Co-Chair: Andrea Calimera, Politecnico di Torino, IT, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Paolo Amato, Micron, IT, Contact
  • Nadine Azemard, LIRMM, FR, Contact
  • Andrea Bartolini, University of Bologna, IT, Contact
  • Andrea Calimera, Politecnico di Torino, IT, Contact
  • Naehyuck Chang, KAIST, KR, Contact
  • Yiran Chen, Duke University, US, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Francesco Gennaro, STMicroelectronics, IT, Contact
  • Masanori Hashimoto, Osaka University, JP, Contact
  • Hiroshi Nakamura, The University of TOKYO, JP, Contact
  • Alberto Nannarelli, Technical University, DK, Contact
  • Umit Ogras, Arizona State University, US, Contact
  • Davide Rossi, University of Bologna, IT, Contact
  • Donghwa Shin, Department of Computer Engineering, Yeungnam University, KR, Contact
  • Sheldon Tan, University of California at Riverside, US, Contact
  • Pascal Vivet, CEA-Leti, FR, Contact
  • Daniel Wong, University of California, Riverside, US, Contact

Theories, tools and methodologies for power modeling, estimation and optimization for electronics systems, applicable to at all layers of design (hardware, software, systems and cross-layers) with a strong emphasis on "power" as the primary optimization target, ranging from ultra-low power systems to high-performance systems also including energy harvesting, cyber-physical systems, large-scale battery applications (electric vehicles, energy storage systems, etc.), Internet of Things, and Artificial Intelligence.

D10 Temperature and Variability Aware System Design and Optimization (click to open)

Chair: Jose L. Ayala, Complutense University of Madrid, ES, Contact

Co-Chair: Qinru Qiu, Syracuse University, US, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Jose L. Ayala, Complutense University of Madrid, ES, Contact
  • Ronald G. Dreslinski, University of Michigan, US, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Dhireesha Kudithipudi, Rochester Institute of Technology, US, Contact
  • Vasilis Pavlidis, University of Manchester, GB, Contact
  • Qinru Qiu, Syracuse University, US, Contact
  • Marco Domenico Santambrogio, Polimi, IT, Contact
  • Pieter Weckx, IMEC, BE, Contact
  • Marina Zapater Sancho, EPFL, CH, Contact

Theories, tools and methodologies for power modeling, estimation and optimization for electronics systems, applicable to at all layers of design (hardware, software, systems and cross-layers) with a strong emphasis on "power" and "energy" as the primary optimization target, ranging from ultra-low power systems to high-performance systems also including energy harvesting, cyber-physical systems, large-scale battery applications (electric vehicles, energy storage systems, etc.), Internet of Things, and artificial intelligence.

D11 Reconfigurable Computing (click to open)

Chair: Philip Brisk, University of California, Riverside, US, Contact

Co-Chair: Suhaib A. Fahmy, University of Warwick, GB, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Michaela Blott, Xilinx, IE, Contact
  • Philip Brisk, University of California, Riverside, US, Contact
  • Alessandro Cilardo, University of Naples Federico II, IT, Contact
  • Suhaib A. Fahmy, University of Warwick, GB, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Nachiket Kapre, Nanyang Technological University, SG, Contact
  • Bogdan Pasca, Intel, FR, Contact
  • Marco Platzner, University of Paderborn, DE, Contact
  • Hayden So, The University of Hong Kong, HK, Contact
  • Ioannis Sourdis, Chalmers University of Technology, SE, Contact
  • Stephan Wong, TU Delft, NL, Contact

Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data center and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D12 Logical and Physical Analysis and Design (click to open)

Chair: Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT, Contact

Co-Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Luca Amaru, Synopsys, US, Contact
  • Luca Amaru, EPFL, IT, Contact
  • Anna Bernasconi, Universita' di Pisa, IT, Contact
  • Luca Daniel, M.I.T., US, Contact
  • Alper Demir, Koc University, TR, Contact
  • Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Jose Monteiro, INESC-ID, Técnico, U Lisboa, PT, Contact
  • Rajeev Murgai, Synopsys India Pvt. Ltd., IN, Contact
  • Farhana Sheikh, Intel Corporation, US, Contact
  • Luis Miguel Silveira, INESC-ID/IST, PT, Contact
  • Mathias Soeken, Integrated System Laboratory – EPFL, CH, Contact
  • Christos Sotiriou, Department of Electrical and Computer Engineering, University of Thessaly, GR, Contact
  • Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT, Contact
  • Wenjian Yu, Tsinghua University, CN, Contact

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D13 Emerging Design Technologies for Future Computing (click to open)

Chair: Aida Todri-Sanial, CNRS-LIRMM/University of Montpellier, FR, Contact

Co-Chair: Subhasish Mitra, Stanford University, US, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Yuanqing Cheng, Beihang University, CN, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Elena Gnani, University of Bologna, IT, Contact
  • Mariagrazia Graziano, Politecnico di Torino, IT, Contact
  • Marc Heyns, IMEC, BE, Contact
  • Subhasish Mitra, Stanford University, US, Contact
  • Arijit Raychowdhury, Georgia Institute of Technology, US, Contact
  • Max Shulaker, MIT, US, Contact
  • Aida Todri-Sanial, CNRS-LIRMM/University of Montpellier, FR, Contact
  • Marleen van der Veen, imec, BE, Contact
  • Walter Weber, NaMLab gGmbH and CfAED, DE, Contact

Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).

D14 Emerging Design Technologies for Future Memories (click to open)

Chair: Jean-Michel Portal, Aix-Marseille University, FR, Contact

Co-Chair: Pierre-Emmanuel Gaillardon, University of Utah, US, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Franco Fummi, Università di Verona, IT, Contact
  • Pierre-Emmanuel Gaillardon, University of Utah, US, Contact
  • Arne Heittman, RWTH Aachen University, DE, Contact
  • Yu Hua, Huazhong University of Science and Technology, CN, Contact
  • Shahar Kvatinsky, Technion, IL, Contact
  • Alexandre Levisse, EPFL, CH, Contact
  • Pascal Meinerzhagen, Intel Circuit Research Lab, US, Contact
  • Michael Niemier, University Of Notre Dame, US, Contact
  • Jean-Philippe Noel, CEA-Leti, FR, Contact
  • Jean-Michel Portal, Aix-Marseille University, FR, Contact
  • Stefan Slesazeck, NaMLab gGmbH, DE, Contact
  • Elena Ioana Vatajelu, TIMA/CNRS/Université de Grenoble-Alpes, FR, Contact
  • Chengmo Yang, University of Delaware, US, Contact
  • Hao Yu, Nanyang Technological University, SG, Contact
  • Weisheng Zhao, Beihang University, CN, Contact

Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.


Track A: Application Design (click to open)

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topics

A1 Power-efficient and Sustainable Computing (click to open)

Chair: Muhammad Shafique, Vienna University of Technology (TU Wien), AT, Contact

Co-Chair: Baris Aksanli, San Diego State University, US, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Baris Aksanli, San Diego State University, US, Contact
  • Luca Benini, University Of Bologna, IT, Contact
  • Thidapat Chantem, Virginia Polytechnic Institute and State University, US, Contact
  • Jungwook Choi, IBM T. J. Watson Research Center, US, Contact
  • william fornaciari, Politecnico di Milano - DEIB, IT, Contact
  • X. Sharon Hu, University of Notre Dame, US, Contact
  • Hai (Helen) Li, Duke University/TUM-IAS, US, Contact
  • Saibal Mukhopadhyay, Georgia Institute of Technology, US, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Semeen Rehman, Vienna University of Technology (TU Wien), Au, Contact
  • Muhammad Shafique, Vienna University of Technology (TU Wien), AT, Contact
  • Yanzhi Wang, University of Southern California, US, Contact

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.

A2 Robotics and Industry 4.0 (click to open)

Chair: Paolo Fiorini, University of Verona, IT, Contact

Co-Chair: Torsten Kroeger, Karlsruhe Institute of Technology, DE, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Federica Ferraguti, University of Modena and Reggio Emilia, IT, Contact
  • Paolo Fiorini, University of Verona, IT, Contact
  • Torsten Kroeger, Karlsruhe Institute of Technology, DE, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Ulrike Thomas, Technical University of Chemnitz, DE, Contact
  • Andrea Zanchettin, Politecnico di Milano, IT, Contact

Bringing together robotics and machine learning concepts requires research and development efforts in interdisciplinary domains. With Industry 4.0 and its goal of adding utility value through data analytics and optimiztion, the Topic "Robotics and Industry 4.0" will remain at the core of the value creation chain during the next decade. The topic covers the field of robotics on topics from sensors and sensory interpretations to kinematics in motion planning, from distributed software concepts for data collection and analysis to large-scale machine learning algorithms, and sensor-based robot and machine control to safe human-robot interaction concepts.

A3 Automotive Systems and Smart Energy Systems (click to open)

Chair: Davide brunelli, University of Trento, IT, Contact

Co-Chair: Sebastian Steinhorst, Technical University of Munich, DE, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • David Boyle, Imperial College London, GB, Contact
  • Davide brunelli, University of Trento, IT, Contact
  • Dip Goswami, Eindhoven University of Technology, NL, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Massimo Poncino, Politecnico di Torino, IT, Contact
  • Selma Saidi, Hamburg University of Technology, DE, Contact
  • Sebastian Steinhorst, Technical University of Munich, DE, Contact
  • Dirk Ziegenbein, Robert Bosch GmbH, DE, Contact

Design experiences for automotive systems, energy-neutral embedded systems, smart energy systems (from uW to microgrid), and related Cyber-Physical applications. Topics of interest include: transient computing; energy harvesting circuits; MEMS; integrated sensors and transducers; RF architectures; in-vehicle networks; systems for electric vehicles; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; hardware solutions for runtime system management such as self-diagnostics and repair; energy generation; battery management, and renewable energy subsystems; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Augmented Living and Personalized Healthcare (click to open)

Chair: Theocharis Theocharides, University of Cyprus, CY, Contact

Co-Chair: Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Amir Aminifar, Swiss Federal Institute of Technology in Lausanne (EPFL), CH, Contact
  • Guillermo Botella, Complutense University of Madrid, ES, Contact
  • Daniela De Venuto, Politecnico di Bari, IT, Contact
  • Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT, Contact
  • Michele Magno, ETH Zurich, CH, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Ioannis Papaefstathiou, Technical university of Crete, GR, Contact
  • Theocharis Theocharides, University of Cyprus, CY, Contact

Design experiences covering the use of body area networks, assistive and wearable technologies, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management ; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness ; embedded and edge-based machine learning for augmented living.

A5 Secure Systems, Circuits, and Architectures (click to open)

Chair: Ingrid Verbauwhede, KU Leuven - COSIC, BE, Contact

Co-Chair: Lionel Torres, University of Montpellier, FR, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Bossuet Lilian, University of St. Etienne, FR, Contact
  • Wayne Burleson, U Massachusetts Amherst, US, Contact
  • Ray Cheung, City University of Hong Kong, HK, Contact
  • Lucas Davi, University of Duisburg-Essen, DE, Contact
  • Aurélien Francillon, EURECOM, FR, Contact
  • Frank Gurkaynak, ETH Zurich, CH, Contact
  • Marcel Medwed, NXP Semiconductors Austria GmbH, AT, Contact
  • Amir Moradi, Ruhr-Universität Bochum, DE, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Thomas Poeppelmann, Infineon Technologies AG, DE, Contact
  • Patrick Schaumont, Virginia Tech, US, Contact
  • Lionel Torres, University of Montpellier, FR, Contact
  • Ingrid Verbauwhede, KU Leuven - COSIC, BE, Contact

Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; emerging technologies for secure circuits and architectures, novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Self-adaptive and Learning Systems (click to open)

Chair: Antonio Miele, Politecnico di Milano, IT, Contact

Co-Chair: Gilles Sassatelli, LIRMM CNRS / University of Montpellier 2, FR, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Giovanni Beltrame, École Polytehcnique de Montréal, CA, Contact
  • Diana Goehringer, TU Dresden, DE, Contact
  • Geoff Merrett, University of Southampton, GB, Contact
  • Antonio Miele, Politecnico di Milano, IT, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Andy Pimentel, University of Amsterdam, NL, Contact
  • Amir M. Rahmani, University of California, Irvine, US, Contact
  • Gilles Sassatelli, LIRMM CNRS / University of Montpellier 2, FR, Contact

Self-adaptive systems, algorithms and techniques for run-time decision-making targeting various optimization goals such as compute performance, energy/power-efficiency or reliability and considering various architectural platforms, such as high-performance compute nodes, power-constrained edge computing technologies and reconfigurable systems. Topics of interests include: adaptive strategies for runtime resource management; application, design and tuning of machine learning techniques for offline and/or online modeling, prediction/forecasting and control of self-adaptive systems; hybrid offline/online techniques for online decision-making; context-aware adaptation strategies and mechanisms; application of diverse data mining, modeling and optimization techniques (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive and learning systems.

A7 Applications of Emerging Technologies (click to open)

Chair: Andy Tyrrell, University of York, GB, Contact

Co-Chair: Yu Wang, Nanjing University of Posts and Telecommunications, CN, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Armin Alaghi, University of Washington, US, Contact
  • Krish Chakrabarty, Duke University, US, Contact
  • Jie Han, University of Alberta, CA, Contact
  • Jim Harkin, Ulster University, GB, Contact
  • Tsung-Yi Ho, National Tsing Hua University, TW, Contact
  • Li Jiang, Shanghai Jiao Tong University, CN, Contact
  • Paul Kaufmann, University of Paderborn, DE, Contact
  • Bing Li, TU München (TUM), DE, Contact
  • yongpan liu, tsinghua university, CN, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Lukas Sekanina, Brno University of Technology, CZ, Contact
  • Martin Albrecht Trefzer, University of York, GB, Contact
  • Andy Tyrrell, University of York, GB, Contact
  • Yu Wang, Nanjing University of Posts and Telecommunications, CN, Contact
  • Robert Wille, Johannes Kepler University Linz, AT, Contact
  • Hailong Yao, Tsinghua University, CN, Contact

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers (click to open)

Chair: Fabien Clermidy, CEA-Leti, FR, Contact

Co-Chair: Norbert Wehn, University of Kaiserslautern, DE, Contact

Track-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Alexandre Arriordaz, Mentor Graphics, US, Contact
  • Fabien Clermidy, CEA-Leti, FR, Contact
  • Mohamed Ibrahim, Duke University, US, Contact
  • Doris Keitel-Schulz, Infineon AG, DE, Contact
  • Enrico Macii, Politecnico di Torino, IT, Contact
  • Emil Matus, Technische Universität Dresden, DE, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Norbert Wehn, University of Kaiserslautern, DE, Contact

Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.


Track T: Test and Dependability (click to open)

covers all test, design-for-test, relia bility, and designfor-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Topics

T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability (click to open)

Chair: Said Hamdioui, Delft University of Technology, NL, Contact

Co-Chair: Jose Pineda, NXP Semiconductors, NL, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Antonio Rubio, UPC, ES, Contact
  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Said Hamdioui, Delft University of Technology, NL, Contact
  • Naghmeh Karimi, University of Maryland, Baltimore County, US, Contact
  • Kuen-Jong Lee, National Cheng Kung University, TW, Contact
  • Hans Manhaeve, Ridgetop Europe, BE, Contact
  • Jose Pineda, NXP Semiconductors, NL, Contact
  • Christian Sauer, Cadence Design Systems GmbH, DE, Contact
  • Adit Singh, Auburn University, US, Contact
  • Arnaud Virazel, LIRMM, FR, Contact
  • Hank Walker, Texas A&M University, US, Contact
  • Yizi Xing, NXP, NL, Contact

Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

T2 Test Generation, Test Architectures, Design for Test, and Diagnosis (click to open)

Chair: Patrick Girard, LIRMM, FR, Contact

Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Davide Appello, STMicroelectronics, IT, Contact
  • Bernd Becker, University of Freiburg, DE, Contact
  • Paolo Bernardi, Politecnico di Torino, IT, Contact
  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Patrick Girard, LIRMM, FR, Contact
  • Erik Larsson, Lund University, SE, Contact
  • Daniel Tille, Infineon Technologies AG, DE, Contact
  • Jerzy Tyszer, Poznan University of Technology, PL, Contact

Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, debug and post silicon validation; machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

T3 Microarchitecture-Level Dependability (click to open)

Chair: Jaume Abella, Barcelona Supercomputing Center (BSC-CNS), ES, Contact

Co-Chair: Ramon Canal, UPC, ES, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Jaume Abella, Barcelona Supercomputing Center (BSC-CNS), ES, Contact
  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Ramon Canal, UPC, ES, Contact
  • Stefano Di Carlo, Politecnico di Torino, IT, Contact
  • Nikos Foutris, University of Manchester, GB, Contact
  • Vijay Janapa Reddi, The University of Texas at Austin, US, Contact
  • Alirad Malek, Chalmers University, SE, Contact
  • Brett Meyer, McGill University, CA, Contact
  • Dimitris Nikolos, University of Patras, GR, Contact

Micro/architectures for fault-tolerant systems against permanent, transient and soft errors, including (but not limited to) processors, memories and accelerators; micro/architectural solutions for safety- and mission-critical systems; analysis and evaluation of reliability, availability and maintainability; hardware/software micro/architectural solutions for fault detection, recovery and aging mitigation.

T4 System-Level Dependability (click to open)

Chair: Maria K. Michael, University of Cyprus, CY, Contact

Co-Chair: Georgios Karakonstantis, Queen's University Belfast, GB, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Luca Cassano, Politecnico di Milano, IT, Contact
  • Maksim Jenihhin, Tallinn University of Technology, EE, Contact
  • Maria K. Michael, University of Cyprus, CY, Contact
  • Georgios Karakonstantis, Queen's University Belfast, GB, Contact
  • Sasa Misailovic, UIUC, US, Contact
  • Mihalis Psarakis, University of Piraeus, GR, Contact
  • Ernesto Sanchez, Politecnico di Torino, IT, Contact
  • Rishad Shafik, Newcastle University, GB, Contact
  • Vasileios Tenentes, ARM Cambridge, GB, Contact

HW and SW solutions for availability, reliability and maintainability against permanent, intermittent, transient, and aging phenomena; system level error/fault modeling; dependability analysis and evaluation; beyond worst-case design solutions, reliable and fail-safe system design; on-line test and functional safety; runtime system management for self-diagnostics and repair; system/runtime orchestration of cross-layer solutions, application resilience, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability including fault prediction, tolerance, detection, isolation, and mitigation; solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

DT5 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS (click to open)

Chair: Georges Gielen, KU Leuven, BE, Contact

Co-Chair: Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Manuel Barragan, TIMA Laboratory, FR, Contact
  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Günhan Dündar, Boğaziçi University, TR, Contact
  • Francisco V. Fernandez, IMSE-CNM, CSIC and Univ. Sevilla, ES, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Georges Gielen, KU Leuven, BE, Contact
  • Helmut Gräb, Technische Universität München, DE, Contact
  • Deukhyoun Heo, Washington State University, US, Contact
  • Deukhyoun Heo, Washington State University, US, Contact
  • Nuno Horta, Instituto de Telecomunicações /Instituto Superior Técnico – Universidade de Lisboa, PT, Contact
  • Mark Po-Hung Lin, National Chung Cheng University, TW, Contact
  • Marie-Minerve Louerat, CNRS and University Pierre et Marie Curie, FR, Contact
  • Manoj Sachdev, University of Waterloo, CA, Contact
  • Gerd Vandersteen, Vrije Universiteit Brussel - dept. ELEC, BE, Contact

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT6 Design and Test of Secure Systems (click to open)

Chair: Ilia Polian, University of Stuttgart, DE, Contact

Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact

Track-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Track-Chair: Franco Fummi, Università di Verona, IT, Contact

Topic Members (click to open)

  • Aydin Aysu, University of Texas at Austin, US, Contact
  • Valentina Banciu, Riscure, NL, Contact
  • Lejla Batina, Radboud University Nijmegen, NL, Contact
  • Cristiana Bolchini, Politecnico di Milano, IT, Contact
  • Jean Luc Danger, Télécom ParisTech, FR, Contact
  • Wieland Fischer, Infineon Technologies, DE, Contact
  • Franco Fummi, Università di Verona, IT, Contact
  • Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US, Contact
  • Mike Hutter, Cryptography Research Inc., US, Contact
  • Bilge Kavun Elif, Infineon, Ge, Contact
  • Farinaz Koushanfar, University of California San Diego, US, Contact
  • Roel Maes, Intrinsic-ID, NL, Contact
  • Yiorgos Makris, The University of Texas at Dallas, US, Contact
  • Nele Mentens, KU Leuven, BE, Contact
  • David Oswald, School of Computer Science, University of Birmingham, GB, Contact
  • Ilia Polian, University of Stuttgart, DE, Contact
  • Francesco Regazzoni, ALaRI, CH, Contact
  • Kazuo Sakiyama, The University of Electro-Communications, JP, Contact
  • Matthias Sauer, University of Freiburg, DE, Contact
  • Johanna Sepulveda, TU Munich, DE, Contact

Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks; machine learning for hardware security evaluation .


Track E: Embedded and Cyber-Physical Systems (click to open)

is devoted to the modelling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyberphysical systems, networked systems, and dependable systems.

Track Chair: Valeria Bertacco, University of Michigan, US, Contact

Topics

E1 Real-time and Dependable Systems (click to open)

Chair: Kai Lampka, Electrobit Automotive GmbH, DE, Contact

Co-Chair: Dionisio de Niz, Carnegie Mellon University, US, Contact

Track-Chair: Valeria Bertacco, University of Michigan, US, Contact

Topic Members (click to open)

  • Sebastian Altmeyer, University of Amsterdam, NL, Contact
  • Valeria Bertacco, University of Michigan, US, Contact
  • Marco Caccamo, University of Illinois, US, Contact
  • Dionisio de Niz, Carnegie Mellon University, US, Contact
  • Rolf Ernst, TU Braunschweig, DE, Contact
  • Gerhard Fohler, Technische Universität Kaiserlautern, DE, Contact
  • Leandro Indrusiak, University of York, GB, Contact
  • Hyoseung Kim, University of California, Riverside, US, Contact
  • Adam Lackorzynski, TU Dresden, DE, Contact
  • Kai Lampka, Electrobit Automotive GmbH, DE, Contact
  • Frank Slomka, Ulm University, DE, Contact

Real-time performance modeling, analysis and empirical evaluation; Worst-case performance analysis techniques; Worst-case execution time analysis; Real-time schedulability of multicore systems; Mixed-Criticality scheduling; Real-time operating systems, microkernels and software; Use of hardware virtualization techniques in time critical applications, Power-aware real-time systems; Industrial case studies of real-time, networked and dependable systems; Adaptive real-time systems; Dependable systems including safety and criticality; Network control and QoS for embedded applications;

E2 Embedded Systems for Deep Learning (click to open)

Chair: Akash Kumar, Technische Universitaet Dresden, DE, Contact

Co-Chair: Sander Stuijk, Eindhoven University of Technology, NL, Contact

Track-Chair: Valeria Bertacco, University of Michigan, US, Contact

Topic Members (click to open)

  • Valeria Bertacco, University of Michigan, US, Contact
  • Anup Das, IMEC, NL, Contact
  • Houman Homayoun, George Mason University, US, Contact
  • Akash Kumar, Technische Universitaet Dresden, DE, Contact
  • Sandeep Pande, IMEC-NL, NL, Contact
  • Thomas Preußer, TU Dresden, DE, Contact
  • Abbas Rahimi, ETH Zurich, CH, Contact
  • Sander Stuijk, Eindhoven University of Technology, NL, Contact

Hardware and architectures, software and algorithmic approaches for artifical intelligence, machine learning and deep learning; resource-efficient and/or low-power embedded architectures for deep learning - specialized compute architectures for machine learning systems - approximate architectures for machine learning applications - learning from limited data sets - novel neural networks architectures and concepts - frameworks for probabilistic and deep learning programming - implementation of DNN applications on embedded systems

E3 Model-Based Design, Verification and Security for Embedded Systems (click to open)

Chair: Yliès Falcone, Univ. Grenoble Alpes, Inria, FR, Contact

Co-Chair: Todd Austin, University of Michigan, US, Contact

Track-Chair: Valeria Bertacco, University of Michigan, US, Contact

Topic Members (click to open)

  • Todd Austin, University of Michigan, US, Contact
  • Ezio Bartocci, Vienna University of Technology, AT, Contact
  • Saddek Bensalem, Université Joseph Fourier, FR, Contact
  • Valeria Bertacco, University of Michigan, US, Contact
  • Yliès Falcone, Univ. Grenoble Alpes, Inria, FR, Contact
  • Luca Geretti, University of Verona, IT, Contact
  • Grigore Rosu, UIUC, US, Contact
  • Kristin Yvonne Rozier, NASA Ames Research Center, US, Contact

Verification techniques for embedded ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as security, timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems. Security attacks, protection and analysis of embedded systems' hardware and software.

E4 Embedded Software Architecture, Compilers and Tool Chains (click to open)

Chair: Borzoo Bonakdarpour, McMaster University, CA, Contact

Co-Chair: Eli Bozorgzadeh, Univ. of California, Irvine, US, Contact

Track-Chair: Valeria Bertacco, University of Michigan, US, Contact

Topic Members (click to open)

  • Valeria Bertacco, University of Michigan, US, Contact
  • Nicola Bombieri, University of Verona, IT, Contact
  • Borzoo Bonakdarpour, McMaster University, CA, Contact
  • Eli Bozorgzadeh, Univ. of California, Irvine, US, Contact
  • Georgios Fainekos, Arizona State University, US, Contact
  • Tulika Mitra, National University of Singapore, SG, Contact
  • Anca Molnos, CEA-Leti, Grenoble, FR, Contact
  • Rodolfo Pellizzoni, University of Waterloo, CA, Contact
  • Hiroyuki Tomiyama, Ritsumeikan University, JP, Contact

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, WCET, etc.; Real-time software, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E5 Cyber-Physical Systems Design (click to open)

Chair: Shiyan Hu, Michigan Technological University, US, Contact

Co-Chair: Davide Quaglia, University of Verona, IT, Contact

Track-Chair: Valeria Bertacco, University of Michigan, US, Contact

Topic Members (click to open)

  • Mohammad Al Faruque, University of California Irvine, US, Contact
  • Valeria Bertacco, University of Michigan, US, Contact
  • Mingsong Chen, East China Normal University, CN, Contact
  • Martin Horauer, University of Applied Sciences Technikum Wien, AT, Contact
  • Shiyan Hu, Michigan Technological University, US, Contact
  • Roberto Passerone, Advanced Laboratory on Embedded Systems, IT, Contact
  • Davide Quaglia, University of Verona, IT, Contact
  • qzhu at northwestern [dot] edu, Contact

Modeling, design, analysis, and optimization of Cyber-Physical Systems (CPS) also in case of large-scale cyber physical systems; verification and validation in CPS; safety and security in CPS; modeling, design, and analysis of internet-of-things as CPS; software-intensive CPS; data-mining and CPS; autonomous and semi-autonomous CPS and related issues; socio-technical systems (e.g., empowered consumer and organizational behavior in smart grids) and CPS; cognitive control for CPS; modeling, design and analysis of networked control, switched control, and distributed control systems: control/architecture co-design and architecture-aware controller synthesis.