Technical Programme Committee 2017

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Topic: D11 Logical and Physical Analysis and Design

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments. Parasitic and variation-aware extraction for on-chip interconnect and passives; Macro-modeling, behavioral and reduced order modeling; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate.

Chair: L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact L. Miguel Silveira

Co-Chair: Tiziano Villa, University of Verona, IT, Contact Tiziano Villa

Members: