ET Exhibition Theatre

Start
Tuesday, 2 February 2021 08:50
End
Thursday, 4 February 2021 18:20
Room
Exhibition Theatre
Exhibition Theatre Chair
Jürgen Haase, edacentrum GmbH, Germany

In addition to the conference programme, there will be Exhibition Workshops as part of the exhibition. These workshops will feature an Exhibition Keynote, technical presentations on the state-of-the-art in our industry, tutorials, and as a special highlight two sessions dedicated especially to a young audience.

The Exhibition Theatre sessions are open to conference delegates as well as to exhibition visitors.

1.8 Industrial Design Methods and Tools: Future EDA Applications and Thermal Simulation for 3D

Session Start
Tue, 08:50
Session End
Tue, 09:40
Moderator
Jürgen Haase, edacentrum GmbH, Germany

This Exhibition Workshop features two talks on industrial design methods and tools. It is open to conference delegates as well as to exhibition visitors.

Presentations

1.8.1 Enabling Early and Fast Thermal Simulation for 3D Multi-Die System Designs

Start
08:50
End
09:15
Speaker
Iyad Rayane, Zuken, France
Co-Author
Koga Kazunari, Zuken, France

As design complexity increases with 3DICs and time-to-market becomes a critical component in the automotive, wearables and IoT segments, reducing design cycle time while maintaining accuracy of analysis has become all the more important. To address this, a system level co-design approach in step with multi-physics analysis is presented. To mitigate errors due to manual exchange of data between various engineering teams spread across chip, package and board with design and analysis adding further level of exchange, a design flow incorporating simplification at the layout level is shown. The flow enables various levels of simplified models to be used, wherein data transfer between the complex 3D structures in layout to the thermal analysis tool is automated. The efficacy of the model simplification is verified through a test case showing comparable results for the simplified and full models.

1.8.2 Future Vision of Altair for EDA Applications

Start
09:15
End
09:40
Speaker
Philippe Le Marrec, Altair, France

Nowadays, design of EDA applications are not only focused on hardware/software parts and need team collaborations. In many cases as in mechatronic, powertrain and control systems, the environment has to be used with the design itself at different level of abstraction. Altair is providing environments which help users to design these multi-physics environments and interact with dedicated solvers. Cloud solutions and data analytics can also be combined to handle best design tuning for powerful multi-physics simulations.

2.8 Exhibition Keynote on Digital Twins and Invitation to Become a Book Author

Session Start
Tue, 16:00
Session End
Tue, 16:50
Moderator
Jürgen Haase, edacentrum GmbH, Germany

This Exhibition Workshop features an Exhibition Keynote and a tutorial on the publication of research results in a book.

Presentations

2.8.1 Exhibition Keynote - Digital Twin: the Future Is Now

Start
16:00
End
16:30
Speaker
Thomas Heurung, Siemens EDA, Germany

Virtually every discussion on business trends talks about digitalization—whether it's the digital thread, digital twin, the digital enterprise, or the digitalization of everything. The goal is to harness the power of the exponential to integrate data in unprecedented ways to deliver new value and performance. As a result, the next generation of SoCs will be driven by business workloads and energy efficiencies, where software performance will define semiconductor success.

That is why a digital twin is becoming a necessity to virtually verify and validate the system performance of SoCs both pre-silicon and then throughout the lifecycle of the SoC. Thomas Heurung, technical director Europe for Siemens EDA, will explain how the digital twin is helping to drive Tera-scale IC and application systems. First by accelerating design creation of custom accelerators.Then, by supporting the shift-left in SoC verification, leading to true system validation from IP to software to systems. And ultimately the digital twin enables a digitalization of the SoC environment both pre-silicon and throughout the lifecycle of the IC.

2.8.2 Book Publishing 101: The Why, How and What

Start
16:30
End
16:50
Speaker
Charles Glaser, Springer Nature, United States

Are you interested in learning more about the why, how (and what) of publishing a book? Publishing a book is a powerful tool, allowing you to communicate your ideas to a global audience, building your reputation in the field and accelerating your career. Join this upcoming webinar to hear from Springer Nature Editorial Director, Charles Glaser, about the stages in the publishing process and how Springer have helped many authors just like you, publish a book.  Q&A will follow to answer all your book publishing questions.

3.8 Industrial Design Methods and Tools: RISC-V

Session Start
Tue, 17:30
Session End
Tue, 18:20
Moderator
Jürgen Haase, edacentrum GmbH, Germany

This Exhibition Workshop features industrial design methods and tools. It is open to conference delegates as well as to exhibition visitors.

Presentations

3.8.1 Andes RISC-V Processor IP Solutions

Start
17:30
End
17:55
Speaker
Florian Wohlrab, Andes Technology, Taiwan

The SoC industry has seen the fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. To serve the market, Andes has developed a rich portfolio of AndesCore processor IPs already used in the above scenarios. They include compact single-issue cores to feature-rich Linux-capable superscalar cores, cacheless single cores to cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. Based on the solid foundation, Andes continues to enrich our product offerings for higher performance efficiency as well as more flexible configurations.

In this talk, we will first give an overview of Andes existing V5 RISC-V processor lineup and present examples of how V5 processors are used in SoC. Then, we will introduce V5 IPs newly added to Andes processor portfolio, the associated software support and their performance data. We will provide an update of Andes Custom Extension™ (ACE) and show how it can further accelerate control and data paths in applications.

6.8 How STM32 Enables Digital Transformation in Industries

Session Start
Wed, 09:00
Session End
Wed, 10:20
Moderator
Jürgen Haase, edacentrum GmbH, Germany
Organizer
Marcello Coppola, STMicroelectronics, France
Organizer
Antonio Lionetto, STMicroelectronics, Italy

One of the most demanding challenges for European industry is the digital transformation of Startups, SMEs and Midcaps. FED4SAE, a program funded by the EU as part of its Horizon 2020 initiative, facilitates access to leading technologies, competencies, and industrial platforms. The session speakers will demonstrate in a pragmatic way how the STM32 microcontroller and its ecosystem have enabled Bettair, Energica Motor Company, Safecility and Zannini to address technical challenges in Smart City, Building Safety, FIM MotoE™ World Cup and Industry4.0. You will learn more about these success stories and what STM32 really means for:

  • Bettair - who will present full cycle development of a complete solution to monitor in real-time the air quality of urban areas
  • Energica Motor Company - who will share The Energica LPWAN Low Power EV Battery Monitor System used in FIM MotoE™ World Cup
  • Safecility - who will present how to Enhance Building Safety across Europe through IoT Automation
  • Zannini - who will show an integrated system for monitoring and controlling industrial machines.
Presentations

6.8.1 Introduction: How STM32 Enables Digital Transformation in Industries

Start
09:00
End
09:08
Speaker
Marcello Coppola, STMicroelectronics, France

6.8.2 Energica LPWAN Low Power EV Battery Monitor System

Start
09:08
End
09:26
Speaker
Giovanni Gherardi, Energica Motor Company, Italy

6.8.3 Air-Quality Monitoring System via LoRaWAN Network

Start
09:26
End
09:44
Speaker
Leonardo Santiago , Bettair Cities, Spain
Speaker
Jaume Ribot, Bettair Cities, Spain

6.8.4 Enhancing Building Safety Across Europe Through IoT Automation Built on STM32: How Safecility Deliver IoT Emergency Lighting

Start
09:44
End
10:02
Speaker
Cian O Flaherty, Safecility, Ireland

6.8.5 An Integrated System for Monitoring and Controlling Industrial Machines

Start
10:02
End
10:20
Speaker
Lorenzo Zampetti, Z4tec, Italy

7.8 ICT Innovation Funding for Manufacturing SMEs

Session Start
Wed, 16:00
Session End
Wed, 16:50
Moderator
Jürgen Haase, edacentrum GmbH, Germany
Organizer
Maria Roca, Fundingbox, Poland
Organizer
Irina Frigioiu, Fundingbox, Poland

I4MS initiative is supporting EU funded projects that are developing solutions that may be of interest to any company for their digital transformation, in any region in Europe specially those lagging behind.
I4MS offers platforms and service for digital transformation to manufacturing SMEs. Different EU projects and DIHs offer solutions for companies to improve their production processes, products or business models with digital technologies. Although these marketplaces have a high potential to offer useful services to certain companies, DIHs should increase their role raising awareness on the available technologies and benefits of the digital transformation. DIHs can help SMEs select the appropriate tools or services for their digital transformation needs.
This session will present the technologies and funding opportunities offered to manufacturing SMEs. A total of 35Million€ will be distributed in the next 2,5 years. Open calls will start in January 2021 and manufacturing SMEs will have the opportunity to receive funding and technological support from the following projects:

Presentations

7.8.1 Presentation of I4MS Phase 4 initiative

Start
16:00
End
16:03
Speaker
Maria Roca, Fundingbox, Poland

7.8.2 Better Factory project presentation & Open Call opportunities

Start
16:03
End
16:10
Speaker
Anca Marin, FundingBox, Poland

7.8.3 Change2Twin project presentation & Open Call opportunities

Start
16:10
End
16:17
Speaker
Tor Dokkenn, SINTEF, Norway

7.8.4 DigITBrain project presentation & Open Call opportunities

Start
16:17
End
16:24
Speaker
Andreas Ocklenburg, cloudSME, Germany
Speaker
Andrea Hanninger, cloudSME, Germany

7.8.5 KITT4SMEs project presentation & Open Call opportunities

Start
16:24
End
16:31
Speaker
Davorka Moslac, Innovation Centre Nikola Tesla, Croatia

7.8.6 VOJEXT project presentation & Open Call opportunities

Start
16:31
End
16:38
Speaker
Maria Roca, Fundingbox, Poland

7.8.7 I4MS Phase 3 success story

Start
16:38
End
16:45
Speaker
Andreas Ocklenburg, cloudSME, Germany
Speaker
Andrea Hanninger, cloudSME, Germany

7.8.8 Closing

Start
16:45
End
16:50
Speaker
Maria Roca, Fundingbox, Poland

8.8 Industrial Design Methods and Tools: Multidimensional Design Reuse and Extended Role of Test for Automotive

Session Start
Wed, 17:30
Session End
Wed, 18:20
Moderator
Jürgen Haase, edacentrum GmbH, Germany

This Exhibition Workshop features two talks on industrial design methods and tools. It is open to conference delegates as well as to exhibition visitors.

Presentations

8.8.1 Earlier SoC Integration with a Multidimensional Design Reuse

Start
17:30
End
17:55
Speaker
Chouki Aktouf, Defacto Technologies, France

SoC design starts by design assembly connecting IP blocks which is just the beginning of the integration process. The difficult part is reaching the best possible PPA (Power, Performance, Area) combination within tight deadlines, while keeping engineering costs under control. In the conventional EDA (Electronic Design Automation) design flow, each task (power consumption, architecture, testing, etc.) is performed separately by an ultra-specialized team of engineers and significant design time is lost in iteration loops. The number of iterations has a great impact on the cost and time frame of the whole project.

This presentation will illustrate how to start SoC Build process much earlier compared to traditional design flows. Using a joint API handling a variety of design domains and design formats including RTL, constraints, power, physical, test, etc. Such API allows non design experts to take important design.

Also, a new dimension of design extraction is presented with a focus on “Power SoC Integration”. It is shown how the design reuse ratio is augmented by keeping engineering cost reasonably low.

8.8.2 Extending the Role of Test to meet Automotive Safety and Security Requirements

Start
17:55
End
18:20
Speaker
Lee Harrison, Siemens EDA, United Kingdom

The role of test is expanding from its traditional role into one that includes managing the entire silicon lifecycle. To ensure that ICs work safely and as expected throughout their operational life, the industry needs to expand from production test to a model that includes ongoing monitoring for defects, degradations, bugs, attacks, and use case surprises.

11.8 Industrial Design Methods and Tools: Neural Network Design

Session Start
Thu, 09:30
Session End
Thu, 10:20
Moderator
Jürgen Haase, edacentrum GmbH, Germany

This Exhibition Workshop features industrial design methods and tools. It is open to conference delegates as well as to exhibition visitors.

Presentations

11.8.1 Automating Tiny Neural Network Design with MCU Deploy-ability in the Loop

Start
09:30
End
10:20
Speaker
Danilo Pau, STMicroelectronics, Italy

Tiny Machine Learning (TinyML) is a growing, widely popular community focusing on the deployment of Deep Learning (DL) models on microcontrollers (MCUs). To run a trained DL model on an MCU, developers must have the necessary skills to handcraft network topologies and associated hyperparameters to fit a wide range of hardware requirements including operating frequency, embedded SRAM and embedded Flash memory along with the corresponding power consumption requirements.

Unfortunately, a hand-crafted design methodology poses multiple challenges: 1) AI and embedded developers exhibit different orthogonal skills, which do not meet each other during the development of AI applications until their validation in an operational environment 2) Tools for automated network design often assume virtually unlimited resources (typically deep networks are trained on cloud- or GPU-based systems) 3) The time-to-market from conception to realization of an AI system is usually quite long. Consequently, mass market adoption of AI technologies at the deep edge is jeopardized.

Our solution is based on Sequential Model Based Optimization (SMBO) – aka Bayesian Optimization (BO) – that is the standard methodology for Automated Machine Learning (AutoML) and Neural Architecture Search (NAS). Although AutoML and NAS are successfully applied on large GPU/Cloud platforms (i.e., some AutoML/NAS tools are commercialized by Google, Amazon and Microsoft), their application is still an issue in the case of tiny devices, such as MCUs. Our approach, instead, includes “deployability” constraints – related to the hardware resources of the MCUs – into the hyperparameter optimization process, leading to this new “AutoTinyML” perspective.

This talk will present our approach, along with its pros and cons with respect to multi-objective optimization (usually adopted to reduce resource usage on cloud). A set of relevant results will be presented and discussed, providing an overview of the next open challenges and perspectives in the AutoTinyML field.