This track addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.
Track Chair: Ayse Coskun, Boston University, US, Contact
Topics
Chair: Ingo Sander, KTH Royal Institute of Technology, SE, Contact
Co-Chair: Andreas Gerstlauer, The University of Texas at Austin, US, Contact
Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; concurrency and communication models; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; performance modeling; timing analysis; predictive and learning-based models; system-level platform and architecture models and simulation.
Chair: Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact
Co-Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR, Contact
High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for HW-SW co-design and partitioning; control and data flow analysis; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation, and binding techniques; multi-objective optimization techniques (e.g., performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems.
Chair: Valeria Bertacco, University of Michigan, US, Contact
Co-Chair: Graziano Pravadelli, University of Verona, IT, Contact
Simulation-based and semi-formal validation and verification of SoCs, MPSoCs, and emerging architectures at any level (from system to circuits), including digital, analog, interconnect or mixed-signal components; testbench and assertion generation and qualification; checker synthesis and optimization; multi-domain and mixed-critical simulation techniques; acceleration-driven and emulation-based approaches for verification and validation; simulation-based pre- and post-silicon diagnosis and debugging solutions; validation and verification for IoT and cloud infrastructures; validation and verification using artificial intelligence or machine learning techniques.
Chair: Christoph Scholl, University Freiburg, DE, Contact
Co-Chair: Armin Biere, Johannes Kepler University Linz, AT, Contact
Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, decomposition techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis.
Chair: Andrè Ivanov, University of British Columbia, CA, Contact
Co-Chair: Georges Gielen, KU Leuven, BE, Contact
Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; HW description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.
Chair: Ilia Polian, University of Stuttgart, DE, Contact
Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact
Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks.
Chair: Luca Carloni, Columbia University, US, Contact
Co-Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
Architecture, design methodologies, and modeling techniques for NoC, including: topology, switching, routing and flow control; NoC service frameworks for Quality-of-Service, security, and power management; techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; integration of external interfaces or memory controllers with NoCs; cache-coherent NoCs; HW-SW communication abstractions; component-based modeling; platform-based design and methodologies; NoC design space exploration frameworks; programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).
Chair: Eli Bozorgzadeh, Univ. of California, Irvine, US, Contact
Co-Chair: Francisco Cazorla, Barcelona Supercomputing Center and IIIA-CSIC, ES, Contact
Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, safety, and timing predictability.
Chair: Alberto Macii, Politecnico di Torino, IT, Contact
Co-Chair: Naehyuck Chang, KAIST, KR, Contact
Algorithms, techniques, and tools for modeling, estimating, or optimizing power consumption of electronic systems, applicable at all levels of the design (HW, SW, or system level), including: dynamic power management; leakage current minimization; design flows and circuit architectures for ultra-low power consumption; energy harvesting; battery modeling and design.
Chair: Giovanni Ansaloni, USI Lugano, CH, Contact
Co-Chair: Jose L. Ayala, Complutense University of Madrid, ES, Contact
Methods, techniques, and architectures for counteracting circuit and system variability due to manufacturing process, temperature, or aging effects, including: design-time and runtime temperature, variability, and reliability management of SoCs and multi-core platforms (both at HW and SW level); modeling and optimization approaches for manufacturing-induced or temperature variations; modeling and optimization methods targeting degradation mechanisms in emerging integration and manufacturing technologies (e.g., 3D stacking).
Chair: Fabrizio Ferrandi, Politecnico di Milano, IT, Contact
Co-Chair: Florent de Dinechin, INSA-Lyon, FR, Contact
Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; reconfigurable computing for high-performance computers and data centers; statically and dynamically reconfigurable and reprogrammable systems and components; FPGA architectures and FPGA circuit design; design methods and tools for reconfigurable computing and communication systems.
Chair: Tiziano Villa, Dipartimento d'Informatica, Universita' di Verona, IT, Contact
Co-Chair: Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.
Chair: Aida Todri-Sanial, CNRS-LIRMM/University of Montpellier, FR, Contact
Co-Chair: Walter Weber, NaMLab gGmbH and CfAED, DE, Contact
Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).
Chair: Jean-Michel Portal, Aix-Marseille University, FR, Contact
Co-Chair: Pierre-Emmanuel Gaillardon, University of Utah, US, Contact
Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.
This track is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow's silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.
Track Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
Topics
Chair: Muhammad Shafique, TU Wien, AT, Contact
Co-Chair: Baris Aksanli, San Diego State University, US, Contact
Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.
Chair: Steffen Paul, University Bremen, DE, Contact
Co-Chair: Theocharis Theocharides, University of Cyprus, CY, Contact
Application design experiences for communication, multimedia, and consumer systems such as smartphones, smart-books/tablets, photo and video cameras, including: digital integrated circuit design of flexible baseband processing systems; intellectual properties for wireless communication, design challenges for SW-defined/cognitive radio systems; embedded systems design in the field of audio, video, and computer vision domains; embedded IP and processor design; sensor networks for dense IoT environments (e.g., Industry 4.0 or smart homes/cities).
Chair: Davide Brunelli, University of Trento, IT, Contact
Co-Chair: Sebastian Steinhorst, Technical University of Munich, DE, Contact
Design experiences for automotive systems, energy scavenging and harvesting for energy-neutral embedded systems, smart energy systems (from small to microgrid), and related applications. Topics of interest include: integrated circuits; MEMS; integrated sensors and transducers; RF architectures; in-vehicle networks; systems for electric vehicles; networks of systems; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; hardware solutions for runtime system management such as self-diagnostics and repair; energy generation; novel energy harvesting, battery management, and renewable energy subsystems; optimization of system energy efficiency in the context of automotive or smart energy applications.
Chair: Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT, Contact
Co-Chair: Joaquín Recas, Computer Science Faculty, Complutense University of Madrid, ES, Contact
Design experiences covering the use of IoT, wireless body sensor networks, assistive and wearable technologies for healthcare, rehabilitation and wellness. Topics of interest include: technologies and application-specific design methodologies (including approximate or significance-driven computing) for ultra-low/zero power systems for personal vital sign monitoring (such as heart rate, fitness devices); body area networks; mobile systems for motor disorder assessment and rehabilitation; wearable and edge computing technologies and designs; devices and systems for personal health and personalized medicine; ambient assisted living technologies; innovative nano-technologies for both non-intrusive or implantable miniaturized sensors and actuators, smart spaces for youngsters, elderly, or impaired users; technologies for motor disorders; personal health devices and assistive technology; power management, on-board performance optimization and networking technologies for body area networks; and ambient intelligence in wellness, healthcare, and fitness.
Chair: Tim Güneysu, University of Bremen & DFKI, DE, Contact
Co-Chair: Stefan Mangard, Graz University of Technology, AT, Contact
Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and prototypes. Topics of interest include: secure HW architectures; novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip enciphering and integrity checking; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.
Chair: Christian Weis, University of Kaiserslautern, DE, Contact
Co-Chair: Antonio Miele, Politecnico di Milano, IT, Contact
Design experiences in the area of adaptive systems targeting reliability, robustness and variability-aware functionality in practical and industrial applications. Topics of interest include: reliable and reconfigurable system development and optimization; practical application mechanisms and use cases that compensate reliability issues such as aging, variability and temperature; reconfigurable systems and applications; static and dynamic reconfiguration techniques; context-aware applications and self-adaptive architectures.
Chair: Andy Tyrrell, University of York, GB, Contact
Co-Chair: Yu Wang, Tsinghua University, CN, Contact
Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).
Chair: Fabien Clermidy, CEA-Leti, FR, Contact
Co-Chair: Norbert Wehn, University of Kaiserslautern, DE, Contact
Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.
This track covers all test, design-for-test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analog and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.
Track Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact
Topics
Chair: Mehdi Tahoori, Karlsruhe Institute of Technology (KIT), DE, Contact
Co-Chair: Said Hamdioui, TU Delft, NL, Contact
Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.
Chair: Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT, Contact
Co-Chair: Davide Appello, STMicroelectronics, IT, Contact
Algorithms for test pattern generation (TPG); TPG for delay and small-delay faults; TPG for low power; algorithms for test compression and compaction; ATPGs; fault simulation; diagnosis; power issues in testing; test generation for microprocessors, memories, FPGAs and regular structures; algorithms for board and system test; volume diagnosis and yield analysis.
Chair: Sybille Hellebrand, University of Paderborn, DE, Contact
Co-Chair: Jerzy Tyszer, Poznan University of Technology, PL, Contact
Architectures and solutions for design for test, diagnosis, debug, post silicon validation; functional safety; in-system run-time test; BIST and embedded test; power-on self-test; test architectures and infrastructures for memories, FPGAs, 2.5D, 3D, SiP, SoC, NoC, and microprocessors; ATE architectures; test standards (JTAG, IJTAG, 1500, 1687, P1838).
Chair: Jaume Abella, Barcelona Supercomputing Center (BSC-CNS), ES, Contact
Co-Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY, Contact
Fault models; permanent, transient and soft errors; reliability evaluation; space-, time- and information-redundancy solutions for availability, reliability and maintainability; highly-available systems; reliable and fail-safe system design; HW/SW solutions for on-line fault detection, tolerance, recovery, and aging mitigation.
Chair: Andrè Ivanov, University of British Columbia, CA, Contact
Co-Chair: Georges Gielen, KU Leuven, BE, Contact
Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; HW description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.
Chair: Ilia Polian, University of Stuttgart, DE, Contact
Co-Chair: Lejla Batina, Radboud University Nijmegen, NL, Contact
Hardware security primitives, including: cryptographic methods; side channel analysis (includling modeling and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators; HW trojans (attacks, detection, or countermeasures); design-for-trust; test infrastructures for secure devices; trusted manufacturing; counterfeit detection and avoidance; HW tampering attacks and protection; modeling and countermeasures for fault attacks.
This track is devoted to the modeling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked systems, and dependable systems.
Track Chair: Franco Fummi, Universita' di Verona, IT, Contact
Topics
Chair: Kai Lampka, Electrobit Automotive GmbH, DE, Contact
Co-Chair: Dionisio de Niz, Carnegie Mellon University, US, Contact
Real-time programming languages and software; real-time (software) performance analysis, e.g., network calculus, worst case execution time analysis, scheduling and software timing estimation, simulation and measurement-based analysis techniques; real-time system optimization; software for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and mixed-criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications.
Chair: Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg, DE, Contact
Co-Chair: Bjorn De Sutter, Ghent University, BE, Contact
Compiler support for multi-core/many-core architectures, GPUs, CGRAs, FPGAs, accelerators in heterogeneous computing platforms, memory hierarchy including caches, scratchpad, and non-volatile memories; code analysis, optimization, and generation for different metrics (e.g., performance, power/energy, code/data size, reliability, security, WCET, etc.); just-in-time compilation, interpreters, binary translation; compiler support for enhanced debugging, profiling, and traceability; Software tools and techniques for design space exploration (compilers, simulators, synthesis tools); compilation infrastructures for high-level synthesis and domain-specific or streaming languages for embedded systems; software synthesis for IoT, wearables, cyber-physical systems, programmable microfluidics.
Chair: Petru Eles, Linkoping University, SE, Contact
Co-Chair: Borzoo Bonakdarpour, Iowa State University, US, Contact
Verification techniques for embedded and cyber-physical systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems.
Chair: Akash Kumar, Technische Universität Dresden, DE, Contact
Co-Chair: Orlando Moreira, Intel Corporation, PT, Contact
Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; software support for approximate computation and accelerators; software architectures for low power and temperature awareness.
Chair: Shiyan Hu, Michigan Technological University, US, Contact
Co-Chair: Thomas Nolte, MRTC/Mälardalen University, SE, Contact
Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); modeling techniques for large-scale cyber physical systems design and analysis; verification and validation in CPS; safety and cybersecurity in CPS systems; internet-of-things and CPS: modeling, analysis, and design; software-intensive CPS; data-mining and CPS; autonomous and semi-autonomous large-scale CPS and related issues; socio-technical systems (e.g., empowered consumer and organizational behavior in smart grids) and CPS; cognitive control for CPS; modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis.