Topic: T1 Modeling and Mitigation of Defects, Faults, Variability, and Reliability

Identification, characterization and modeling of defects, faults and degradation mechanisms in conventional, advanced and emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT…); defect-based fault analysis; reliability analysis and modeling at device, circuit and component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit and component level;

Chair: Mehdi Tahoori, Karlsruhe Institute of Technology (KIT), DE, Contact

Co-Chair: Said Hamdioui, Delft University of Technology, NL, Contact

Members:

• Vikas Chandra, ARM, US, Contact
• Seiji Kajihara, Kyushu Institute of Technology, JP, Contact
• Bram Kruseman, NXP Semiconductors Netherlands BV, NL, Contact
• Hans Manhaeve, Ridgetop Europe, BE, Contact
• Jose Pineda de Gyvez, NXP Semiconductors, NL, Contact
• Rosa Rodriguez, UPC, ES, Contact
• Antonio Rubio, Universitat Politècnica de Catalunya (UPC), ES, Contact