Topic: D7 Network on Chip

Architecture and modeling techniques for NoC; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security and power management; Techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; Integration of external interfaces/memory controllers with NoCs; Cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; Programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

Chair: Luca Carloni, Columbia University, US, Contact

Co-Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact

Members:

• Fabien Clermidy, COMMISSARIAT A L' ENERGIE ATOMIQUE, FR, Contact
• Masoud Daneshtalab, KTH Royal Institute of Technology, SE, Contact
• Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
• Natalie Enright Jerger, University of Toronto, CA, Contact
• Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
• Paul Gratz, Texas A&M University, US, Contact
• Andreas Hansson, ARM Ltd, GB, Contact
• Ravi Iyer, Intel, US, Contact
• Axel Jantsch, Technische Universität Wien, AT, Contact
• Ajay Joshi, Boston University, US, Contact
• John Kim, KAIST, KR, Contact
• Tushar Krishna, GeorgiaTech, US, Contact
• , Contact
• Fernando Moraes, PUC-RS, BR, Contact
• Umit Ogras, Arizona State University, US, Contact
• Jiang Xu, Hong Kong University of Science and Technology, CN, Contact