Technical Programme Committee 2017
Topic: D6 Power Modeling, Optimization and Low-Power Design
Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Energy harvesting and battery modeling and design.
Chair: Alberto Macii, Politecnico di Torino, IT, Contact
Co-Chair: Naehyuck Chang, Korea Advanced Institute of Science and Technology (KAIST), KR, Contact
Members:
- Andrea Bartolini, University of Bologna, IT, Contact
- Andrea Calimera, Politecnico di Torino, IT, Contact
- William Fornaciari, Politecnico di Milano, IT, Contact
- Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
- Jae-Joon Kim, POSTECH, KR, Contact
- Hiroshi Nakamura, University of Tokyo, JP, Contact
- Alberto Nannarelli, DTU, DK, Contact
- Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
- Salvatore Rinaudo, STMicroelectronics, IT, Contact
- Martha Johanna Sepulveda Florez, Technical University of Munich, DE, Contact
- Donghwa Shin, Department of Computer Engineering, Yeungnam University, KR, Contact
- Sheldon Tan, UC Riverside, US, Contact
- Pascal Vivet, CEA-Leti, FR, Contact
- Yanzhi Wang, Syracuse University, US, Contact
- Chia-Lin Yang, National Taiwan University, TW, Contact
- Shusuke Yoshimoto, Osaka University, JP, Contact