Topic: D7 Power Modeling, Optimization and Low-Power Design

Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Energy harvesting and battery modeling and design.

Chair: Alberto Macii, Politecnico di Torino, IT, Contact

Co-Chair: Naehyuck Chang, Korea Advanced Institute of Science and Technology (KAIST), KR, Contact

Members:

• Antonio Acosta, Univ. of Seville/IMSE, ES, Contact
• Edith Beigne, CEA-Leti Minatec, FR, Contact
• Andrea Calimera, Politecnico di Torino, IT, Contact
• William Fornaciari, Politecnico di Milano, IT, Contact
• Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
• Jae-joon Kim, POSTECH, KR, Contact
• Marisa Lopez-Vallejo, UPM, ES, Contact
• Diana Marculescu, Carnegie Mellon University, US, Contact
• Andrea Marongiu, University of Bologna, IT, Contact
• Seda Memik, Northwestern University, US, Contact
• Hiroshi Nakamura, Graduate School of Information Science and Technology, the University of Tokyo, JP, Contact
• Alberto Nannarelli, Technical University of Denmark, DK, Contact
• Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
• Donghwa Shin, Yeungnam University, KR, Contact
• Tajana Simunic Rosing, UCSD, US, Contact
• Sheldon Tan, UC Riverside, US, Contact
• Chia-Lin Yang, National Taiwan University, TW, Contact