Topic: D12 Logical and Physical Analysis and Design

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments. Parasitic and variation-aware extraction for on-chip interconnect, and passives; Macro-modeling, behavioral and reduced order modeling; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate.

Chair: Patrick Groeneveld, Synopsys, US, Contact

Co-Chair: L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact

Members:

• Valentina Ciriani, University of Milano, IT, Contact
• Luca Daniel, Massachusetts Institute of Technology, US, Contact
• Azadeh Davoodi, University of Wisconsin - Madison, US, Contact
• Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
• Jens Lienig, Technical University of Dresden, DE, Contact
• Igor Markov, University of Michigan, US, Contact
• José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact
• Sven Peyer, IBM, DE, Contact
• Cliff Sze, IBM Austin Research Laboratory, US, Contact
• Tiziano Villa, University of Verona, IT, Contact
• Vladimir Zolotov, IBM T.J. Watson Research Center, US, Contact