DATE 2017 - Call for Papers


DATE 2017 Logo

Conference and Exhibition

March 27-31, 2017, Swiss Tech Convention Center, Lausanne, Switzerland

Call for Papers

Scope of the Event

The 20th DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on both ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software.

Structure of the Event

The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials, workshops, two special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software, and (industrial) design experiences from different application domains, such as automotive, wireless, telecom and multimedia applications. The organization of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community. Special space will also be allocated for EU-funded projects to show their results. More details are given on the DATE website (

Areas of Interest

Within the scope of the conference, the main areas of interest are: embedded systems, design methodologies, CAD languages, algorithms and tools, testing of electronic circuits and systems, embedded software, applications design and industrial design experiences. Topics of interest include, but are not restricted to:

  • System Specification and Modeling
  • System Design, Synthesis and Optimization
  • Simulation and Validation
  • Design of Low Power Systems
  • Temperature-Aware Design
  • Power Estimation and Optimization
  • Temperature Modeling and Management
  • Emerging Technologies, Systems and Applications
  • Formal Methods and Verification
  • Network on Chip
  • Architectural and Microarchitectural Design
  • Architectural and High-Level Synthesis
  • Reconfigurable Computing
  • Logic and Technology Dependent Synthesis for Deep-Submicron Circuits
  • Physical Design and Verification
  • Analogue and Mixed-Signal Circuits and Systems
  • Interconnect, EMC, EMD and Packaging Modeling
  • Multiprocessor System-on-Chip and Computing Systems
  • Communication, Consumer and Multimedia Systems
  • Transportation Systems
  • Medical, Healthcare and Assistive Technology Systems
  • Energy Generation, Recovery and Management Systems
  • Secure, Dependable and Adaptive Systems
  • Test for Defects, Variability, and Reliability
  • Test Generation, Simulation and Diagnosis
  • Test for Mixed-Signal, Analog, RF, MEMS
  • Test Access, Design-for-Test, Test Compression, System Test
  • On-Line Testing and Fault Tolerance
  • Real-time, Networked and Dependable Systems
  • Compilers and Code Generation for Embedded Systems; Software-centric System Design Exploration
  • Model-based Design and Verification for Embedded Systems
  • Embedded Software Architectures and Principles; Software for MPSoC, Multi/many-core and GPU-based Systems

Submission of Papers

All papers have to be submitted electronically by Sunday September 11, 2016 via:

Papers can be submitted either for standard oral presentation or for interactive presentation. The Programme Committee also encourages proposals for Special Sessions, Tutorials, Friday Workshops, University Booth, PhD Forum and Exhibition Theatre.

Event Secretariat

c/o K.I.T. Group GmbH Dresden

Muenzgasse 2, 01067 Dresden, Germany

Phone: +49 351 4967 541, Fax: +49 351 4956 116

Email: date at kitdresden [dot] de


General Chair: David Atienza, EPFL, Lausanne, Switzerland, david [dot] atienza at epfl [dot] ch
Programme Chair: Giorgio Di Natale, LIRMM, Montpellier, France, giorgio [dot] dinatale at lirmm [dot] fr