UB11 Session 11

Printer-friendly version PDF version

Date: Thursday 17 March 2016
Time: 14:30 - 16:30
Location / Room: Booth 15, Exhibition Area

LabelPresentation Title
Authors
UB11.1MICROTESK ARMV8 EDITION: SPECIFICATION-BASED TEST PROGRAM GENERATOR
Presenter:
Andrei Tatarnikov, Russian Academy of Sciences (RAS), RU
Authors:
Andrei Tatarnikov, Alexander Kamkin and Artem Kotsynyak, Russian Academy of Sciences (RAS), RU
Abstract
This work presents a test program generation tool for ARMv8 microprocessors. The tool consists of two parts: an architecture-independent test program generation core and ARMv8 specifications. The specifications provide information on the instruction set architecture and the memory management unit of an ARMv8 microprocessor. Test programs are generated on the basis of test templates provided by users and testing knowledge extracted from the specifications. Test templates describe scenarios to be covered in terms of test situations, while testing knowledge specifies constraints that should be satisfied in order for these situations to occur. The architecture-independent test program generation core implements a wide range of test generation techniques including random generation, combinatorial generation, constraint solving and symbolic execution. Flexible architecture of the tool allows integrating different generation methods and extending the test generation core with new engines.

Download Paper (PDF)
UB11.2AIPHS: ADAPTIVE PROFILING HARDWARE SUB-SYSTEM
Presenter:
Luigi Pomante, Università degli Studi dell'Aquila, IT
Authors:
Luigi Pomante1, Giacomo Valente2 and Vittoriano Muttillo2
1Università degli Studi dell'Aquila, IT; 2Università Degli Studi Dell'Aquila, IT
Abstract
Run-time monitoring systems on reconfigurable logic have the advantage that they can be customized with respect to specific applications: in the context of automated testing, this can lead to powerful scenarios. This demo presents a smart monitoring system by showing both a customization for stalls identification in a message passing scenario (based on four MicroBlaze that executes a bare-metal FFT application), and a customization for bus utilization monitoring in a symmetric multi-processing system scenario (based on four Leon3 running a custom Linux kernel). The whole development flow (and related prototypal EDA tools), that starts exploiting a library of elements to compose the desired hardware profiler, that leads to the introduction of such a profiler in the target architecture, and that allows profiling data collection and analysis will be shown. Moreover, a comparison among different functionalities will be illustrated. Both systems will be illustrated by using Zynq7000 SoC.

Download Paper (PDF)
UB11.3COMPSOC: VIRTUALISING CONTROL APPLICATIONS ON A DISTRIBUTED COMPSOC PLATFORM
Presenter:
Kees Goossens, Eindhoven University of Technology, NL
Author:
Kees Goossens, Eindhoven University of Technology, NL
Abstract
In our University Booth we will demonstrate that multiple real-time control applications can be developed independently even though they share platform resources. We show that they can run together with other applications on a wireless network of multiple CompSOC platforms, where each platform has multiple processors, NOC, and a complete microkernel, streaming software, and resource management stack. We will also show that (control) applications can be quickly and safely loaded and started without interference to other (real-time control) applications, thus implementing a network of MPSOCs for distributed mixed time-criticality applications.

Download Paper (PDF)
UB11.4CLASH: DIGITAL CIRCUITS IN CλASH
Presenter:
Christiaan Baaij, University of Twente, NL
Authors:
Christiaan Baaij and Jan Kuper, University of Twente, NL
Abstract
CλaSH is a novel compiler system for generating digital circuits as described by a mathematical/functional specification of the architecture. We will demonstrate several applications written in CλaSH: * Tunneling ball device: With a minimal amount of acceleration, a fast spinning metal disk is either sped up or slowed down so that a falling ball can fall through one of the metal disk's two holes. * Music synthesizer and spectrum analyser: An audio CODEC samples music being played from either an MP3 player or a computer. We can apply several digital filters which affect the music. The effects of these filters can be both seen on a monitor, and heard through speakers connected to the FPGA board. * Multi-processor system: The system is used in a compiler construction course, where the compiler is written in the Haskell. Because CλaSH is proper subset of Haskell, students can build and experiment with the compiler and the multi-processor system in the same environment.

Download Paper (PDF)
UB11.5CONTREP: A SINGLE-SOURCE FRAMEWORK FOR UML-BASED MODELLING AND DESIGN OF MIXED-CRITICALITY SYSTEMS
Presenter:
Fernando Herrera, University of Cantabria, ES
Authors:
Fernando Herrera and Eugenio Villar, University of Cantabria, ES
Abstract
Mixed-criticality systems integrate applications, platform resources and requirements with different criticality. A criticality reflects the impact of either a failure of a component or a violation of a requirement, which can range from irrelevant to catastrophic effects. This booth presents the CONTREP framework, which supports UML/MARTE based modeling, analysis and design of mixed-criticality embedded systems. The booth shows a model of a quadcopter control system which integrates safety critical (e.g. flight control), mission-critical (e.g., a video processing payload), and non-critical (e.g., monitoring) functions. The booth shows how mixed-criticality is captured, together with the description of the functional architecture, and of the multi-core embedded platform where the system is implemented; how CONTREP automates different design activities, i.e. model validation, performance assessment and design space exploration, exploiting mixed-criticality information in every case.

Download Paper (PDF)
UB11.6RETRASCOPE: TOOLKIT FOR ANALYSIS AND VERIFICATION OF HDL DESIGNS
Presenter:
Sergey Smolov, Russian Academy of Sciences (RAS), RU
Authors:
Sergey Smolov, Alexander Kamkin and Mikhail Lebedev, Russian Academy of Sciences (RAS), RU
Abstract
Retrascope is an open-source toolkit for Reverse Engineering and TRAnsformation of digital hardware designs described in such hardware description languages as Verilog and VHDL. The toolkit allows analyzing HDL descriptions, reconstructing the underlying models (guarded actions, extended finite state machines, high-level decision diagrams etc.) and using the derived models for test generation, property checking and other tasks. Retrascope is organized as an extendible framework with the ability to add new types of models as well as tools for their analysis and transformation. The primary application domain of the toolkit is functional verification of hardware at the unit level.

Download Paper (PDF)
UB11.7ELECTRO-, STRESS- AND THERMOMIGRATION: THREE FORCES, ONE PROBLEM
Presenter:
Steve Bigalke, Technische Universität Dresden, DE
Authors:
Steve Bigalke and Jens Lienig, Technische Universität Dresden, DE
Abstract
It is well-known that the downscaling of microelectronic structures ("Moore's Law") reduces the reliability due to an increase in potential material migration. Electro-, stress- and thermomigration have been identified as the main causes of materiel dislocation in integrated circuits (ICs). They are driven by current densities, stress and temperature gradients, respectively, but they also depend on common parameters like material constants. While each of these three driving forces causes migration, they can compensate or amplify each other, resulting in various overall material dislocations. These interactions are poorly understood which complicates the prevention of migration processes in ICs. Our software demonstrator presents a basic approach to identify the predominate migration within various circuit conditions including the interaction of all three forces. Our approach can also be adjusted to three-dimensional circuits (3D ICs) and alternating conditions.

Download Paper (PDF)
UB11.8CHIMPANC: CHANGE MANAGEMENT USING CHIMPANC
Presenter:
Jannis Stoppe, DFKI and University of Bremen, DE
Authors:
Jannis Stoppe, Martin Ring and Rolf Drechsler, DFKI and University of Bremen, DE
Abstract
One approach to remedy the issue of increasing complexity in the hardware design process is to provide designers with more abstract languages that allow systems to be designed top-down, starting with an abstract model of the system and its requirements. Several of these languages such as SysML and SystemC are being used today. We propose the Change Impact Analysis and Control Tool (ChImpAnC) to handle these challenges. ChImpAnC extracts the relevant information from the models on the different levels and constructs mappings between them, thus allowing to check consistency and refinements, and moreover calculating the impact of changes. Thus, ChImpAnC ensures that e.g. a written specification or documentation is not made obsolete by changes in the implementation without being warned about it.

Download Paper (PDF)
UB11.9IDDD: AN INTERACTIVE DEPENDABILITY DRIVEN DESIGN SPACE EXPLORATION
Presenter:
Stefan Scharoba, Brandenburg University of Technology Cottbus-Senftenberg, DE
Authors:
Stefan Scharoba, Jacob Lorenz and Heinrich T. Vierhaus, Brandenburg University of Technology Cottbus-Senftenberg, DE
Abstract
Due to the downscaling of transistor feature sizes, today's integrated circuits are much more likely to be affected by transient or permanent faults. In order to still meet certain dependability requirements, many different fault tolerance techniques have been developed, which can handle these faults in the field. Each of these techniques is associated with distinct costs and benefits. As a consequence, finding the fault tolerant implementation of the system that meets the actual requirements best represents a challenging task. We propose a tool that supports this process. It offers a set of hardware based fault tolerance techniques that can be applied to a given VHDL model. Afterwards, costs and benefits of the respective design choice are estimated automatically. Thus several fault tolerant versions of the design can be evaluated and compared with each other without implementing them manually. Finally, the VHDL code of the preferred design candidate can be generated by the tool.

Download Paper (PDF)
UB11.10RESECU_4_AMBRAMS: TOWARDS INCREASED RELIABILITY AND HARDWARE SECURITY USING AMBRAMS
Presenter:
Petr Pfeifer, TU Liberec, CZ
Author:
Petr Pfeifer, TU Liberec, CZ
Abstract
AmBRAMs-The new method and developed advanced Analysis Tool and Framework for Advanced Measurements and Reliability Assessments on Modern Nanoscale FPGAs creates revolutionary new set of tools enables complex lab-on-chip solutions in nanoscale FPGAs.AmBRAMs has been enhanced of advanced measurements and data processing supporting platform identification and security support functionality including tampering detection preferably in modern nanoscale programmable devices.It will be presented on VLIW soft processor cores equipped with a security IP,and showing also POF solutions and related functionality.Detection of power voltage variation using AmBRAMs technology is incorporated in the processor application and demonstrating it on a complex processor system.Presented on 28nm LP or 20nm HP UltraScale Xilinx FPGA devices.The 28nm FPGA solution will also show simple HW adjustments enabling support of power supply change required the demonstrator and for adaptive control presented as well.

Download Paper (PDF)
16:30End of session