UB03 Session 3

Label	Presentation Title Authors
UB03.1	HIGH-END 122GHZ MINIATURE RADAR SENSOR FOR AUTONOMOUS AIRCRAFTS Presenter: Federico Nava, Heinz Nixdorf Institute - Universität Paderborn, DE Authors: Federico Nava¹ and Christoph Scheytt² ¹Heinz Nixdorf Institute - Universität Paderborn, DE; ²Heinz Nixdorf Institute - Paderborn, DE Abstract The importance of high precision sensors, sensors-arrays and the concept of sensor fusion are rising interest in the field of scientific research for autonomous vehicles. For this reason the System and Circuit Technology group at the Heinz Nixdorf Institute is currently developing a highly integrated radar module as a sensor for Unmanned Aerial Vehicle applications. The presented system is composed of a radar IC (130nm SiGe) with in-package antennas and operating frequency of 122GHz mounted on a FLEX-PCB including a CORTEX M4 MCU for a total size of 30x30mm. The presentation will show the FMCW/CW radar functions of the device, allowing the tracking of velocity and distance for multiple objects. The results of the radar measurements will be presented on a screen showing the raw data acquired in time domain and a FFT representation. Different objects will move simultaneously in the area of reception of the sensor. The results of the tracked distances will be then plotted on screen. Download Paper (PDF)
UB03.2	EXTRA-FUNCTIONAL PROPERTY SIMULATION WITH VIRTUAL PLATFORMS Presenter: Ralph Görgen, OFFIS - Intitute for Information Technology, DE Authors: Ralph Görgen, Kim Grüttner and Sören Schreiner, OFFIS - Intitute for Information Technology, DE Abstract The demo shows the usage of virtual platforms and model-based design to perform early analyses of extra-functional properties in a mixed-critical scenario. The application shown is a quadro-copter equipped with a camera system. The copter's flight controller is safety critical; the video processing is less critical. Both parts of the system are implemented in a single chip, a Xilinx ZNQ SoC. The video processing is implemented in the ARM dual-core, the flight controller is realized in the FPGA part and based on two MicroBlaze cores. This platform has been modeled as an OVP-based virtual platform, which is extended by more fine grain timing models as well as power models. Furthermore, it can be coupled with a model of the quadro-copter physics and environment realized in iXtronics CamelView. We will show how to use this setup to analyze timing, power, and temperature behavior of the system and the interference between the high- and low-critical parts with respect to these properties. Download Paper (PDF)
UB03.3	ETEAK: ASYNCHRONOUS DATAFLOWS SYNTHESIS ONTO FPGAS USING THE ETEAK FRAMEWORK Presenter: Mahdi Jelodari Mamaghani, The University of Manchester, GB Authors: Mahdi Jelodari Mamaghani, Jim Garside and Steve Furber, The University of Manchester, GB Abstract We exploit eTeak (De-Elastisation [DATE'15] enabled) to synthesise asynchronous dataflow descriptions in Balsa into synchronous structure loadable onto FPGA. We will be also able to demonstrate the software realisation of the same architecture running on a laptop and let the audience compare the hardware vs. software concurrency. A brief experiment conducted in our recent study where a prime number generator (aka sieve of Eratosthenes) is implemented both in software using the CSP compiler and hardware using eTeak: On average the hardware implementation runs 90-120x faster than its software counterpart while the processor clock speed is almost the same as the hardware clock speed (1.2GHz). This allows us to plan ahead and exploit eTeak toward energy-efficient synthesis. According to EPSRC's research portpolio this work falls under the most growing research subject of "Energy Efficiency" which aims to achieve an energy reduction of 26-43% by exploiting ICT. Download Paper (PDF)
UB03.4	LISA: ENABLING LAYERED INTEROPERABILITY FOR INTERNET OF THINGS THROUGH LISA Presenter: Behailu Shiferaw Negash, University of Turku, FI Authors: Behailu Shiferaw Negash¹, Amir-Mohammad Rahmani¹, Tomi Westerlund¹, Pasi Liljeberg¹ and Hannu Tenhunen² ¹University of Turku, FI; ²University of Turku, FI and Royal Institute of Technology (KTH), SE Abstract There is high expectation towards the changes that come with the implementation of the Internet of Things (IoT). However, this vision is limited by the heterogeneous nature of IoT devices. This led to vertical application silos that are incapable of working together. To ease this problem of heterogeneity, we have developed a lightweight interoperability framework, LISA, to hide variations in communication technology and data formats and provide a uniform API for programmers. LISA is inspired by Network on Terminal Architecture (NoTA), an open framework from Nokia Research Center. There are few frameworks for interoperability of IoT. However, these frameworks fail to address the resource limitations of the majority of IoT devices. To the best of our knowledge, LISA is the first framework designed for resource constrained devices. This demonstration shows LISA in action, helping heterogeneous devices interoperate through a gateway in the fog layer between the devices and the cloud. Download Paper (PDF)
UB03.5	NEURODSP: A MULTI-PURPOSE ENERGY-OPTIMIZED ACCELERATOR FOR NEURAL NETWORKS Presenter: Jean-Marc PHILIPPE, CEA LIST, FR Authors: Jean-Marc PHILIPPE, Alexandre CARBON and Renaud SCHMIT, CEA LIST, FR Abstract Deep Neural Networks (e.g. Convolutional Neural Networks) is a promising approach to design smart machines for a wide range of application domains (automotive, home automation, industry, etc.). Due to their structure, these processing chains are compute intensive and difficult to embed into low power systems. To tackle this challenge, CEA LIST investigated the NeuroDSP hardware accelerator IP, able to be embedded into FPGA- or ASIC-based systems. Providing the system with a dramatic performance/watt ratio improvement, the IP can sustain 450GMACS/W in FDSOI 28nm technology, meeting the requirements of high-end embedded applications. The proposed demonstration features a comparison between three implementations of a CNN processing chain used to detect faces in a large image database. It shows that a single cluster FPGA-based implementation of the NeuroDSP IP at 100MHz is able to outperform both a Raspberry Pi 2 and an Odroid-XU3 board by a factor of respectively 10 and 6 in performance. Download Paper (PDF)
UB03.6	IDDD: AN INTERACTIVE DEPENDABILITY DRIVEN DESIGN SPACE EXPLORATION Presenter: Stefan Scharoba, Brandenburg University of Technology Cottbus-Senftenberg, DE Authors: Stefan Scharoba, Jacob Lorenz and Heinrich T. Vierhaus, Brandenburg University of Technology Cottbus-Senftenberg, DE Abstract Due to the downscaling of transistor feature sizes, today's integrated circuits are much more likely to be affected by transient or permanent faults. In order to still meet certain dependability requirements, many different fault tolerance techniques have been developed, which can handle these faults in the field. Each of these techniques is associated with distinct costs and benefits. As a consequence, finding the fault tolerant implementation of the system that meets the actual requirements best represents a challenging task. We propose a tool that supports this process. It offers a set of hardware based fault tolerance techniques that can be applied to a given VHDL model. Afterwards, costs and benefits of the respective design choice are estimated automatically. Thus several fault tolerant versions of the design can be evaluated and compared with each other without implementing them manually. Finally, the VHDL code of the preferred design candidate can be generated by the tool. Download Paper (PDF)
UB03.7	DIGITALLY DRIVEN TOP-DOWN METHODOLOGY FOR MIXED SIGNAL CIRCUIT DESIGN Presenter: Markus Mueller, University of Heidelberg, DE Authors: Markus Mueller, Maximilian Thuermer and Ulrich Bruening, University of Heidelberg, DE Abstract In this methodology,synthesizable modules and full custom blocks are first described in an HDL in a top-down approach. For analog cells, real number based models are created.Once the complete mixed signal model is done, each cell in the design is completely described concerning interface and behavior. The models then serve as specification for the full custom cell development.Schematics which don't include any primitives are automatically generated from the HDL description by a scripted flow to ensure consistency.Design space exploration can be done fast and very efficient this way. Cells which can be reused at different places in the design are identified and problems arising from interactions on the system level are found early in the design phase.This methodology accelerates the design process significantly, avoids errors and provides higher flexibility for design changes. A digital centric design example of a High Speed SerDes IP is demonstrated using the described methodology. Download Paper (PDF)
UB03.8	GPCDS: AN INTERACTIVE TOOL FOR CREATING SCHEMATIC MODULE GENERATORS IN ANALOG IC DESIGN Presenter: Matthias Greif, Reutlingen University, DE Authors: Matthias Greif and Juergen Scheible, Reutlingen University, DE Abstract While digital design automation is highly developed, analog design automation still remains behind the demands. Previous approaches of circuit creation, which are usually based on optimization algorithms, do not satisfy industrial requirements. A promising alternative is given by procedural approaches, which imitate the solution strategy of a human expert. We are working on parameterized generators (such as PCells) for analog circuit and layout modules, special kinds of such procedures. We present "gPCDS", a novel tool for the creation of schematic generators for analog circuit design. Associated with a common design environment, gPCDS offers a sophisticated interactive design flow for the development of schematic PCells. gPCDS thus substitutes the crucial process of manual code writing by an intuitive graphic-based way of schematic PCell creation. The GUI of gPCDS provides a variety of useful functions, such as defining parameter ranges or placing predefined building blocks. Download Paper (PDF)
UB03.9	PFPSIM: A PROGRAMMABLE FORWARDING PLANE SIMULATOR Presenter: Gordon Bailey, Concordia University, CA Author: Gordon Bailey, Concordia University, CA Abstract We demonstrate PFPSim, a host-compiled simulator for early validation and analysis of packet processing applications on programmable forwarding plane architectures, used in software defined networks. The simulation model is automatically generated from a high-level description of the hardware/software architecture of the forwarding device and the behavioral description of the various modules in the architecture. Our high-level architectural description language is capable of defining many-core network processors as well as reconfigurable pipelines. The behavior of the fixed-function processing elements in the architecture is defined in C++. The code targeted for the processor cores, or reconfigurable pipeline stages, is compiled from P4, an emerging programming language for packet processing applications. Network dataplane programmers can use PFPSim as a virtual prototype to simulate and debug their applications before hardware availability. Download Paper (PDF)
UB03.10	ALPT: A FAST PROTOTYPING METHODOLOGY WITH CONSTRAINED FLOORPLANING ON ANALOG LAYOUT GENERATION Presenter: Po-Cheng Pan, National Chiao Tung University, TW Authors: Po-Cheng Pan, Hung-Wen Huang and Hung-Ming Chen, National Chiao Tung University, TW Abstract Layout generation in the recent analog design is challenging by its critical layout dependent effect (LDE). Based on the same netlist design, different layouts lead distinct performances. Therefore, it is necessary to observe and avoid the LDE during generation. Traditionally, the strategies of analog layout generation mostly count on experienced designers. However, the experience is based on time-consuming manually try-run, which is inefficient and unreliable. In this work, we develop a fast prototyping for analog layout generation. In our approach, we apply a fast floorplanning algorithm, for multi-layout generation and select the feasible results w.r.t. the analog constraints pre-decided. For practical usage, we implement this approach embedded on the EDA-tool so that layout designers are able to design with such prototypes for efficiency. The demonstration includes layout prototyping generation, the integration between our program and EDA-tool and the resulting layout prototypes. Download Paper (PDF)
17:30	End of session

Label

Presentation Title
Authors

UB03.1

HIGH-END 122GHZ MINIATURE RADAR SENSOR FOR AUTONOMOUS AIRCRAFTS
Presenter:
Federico Nava, Heinz Nixdorf Institute - Universität Paderborn, DE
Authors:
Federico Nava¹ and Christoph Scheytt²
¹Heinz Nixdorf Institute - Universität Paderborn, DE; ²Heinz Nixdorf Institute - Paderborn, DE
Abstract
The importance of high precision sensors, sensors-arrays and the concept of sensor fusion are rising interest in the field of scientific research for autonomous vehicles. For this reason the System and Circuit Technology group at the Heinz Nixdorf Institute is currently developing a highly integrated radar module as a sensor for Unmanned Aerial Vehicle applications. The presented system is composed of a radar IC (130nm SiGe) with in-package antennas and operating frequency of 122GHz mounted on a FLEX-PCB including a CORTEX M4 MCU for a total size of 30x30mm. The presentation will show the FMCW/CW radar functions of the device, allowing the tracking of velocity and distance for multiple objects. The results of the radar measurements will be presented on a screen showing the raw data acquired in time domain and a FFT representation. Different objects will move simultaneously in the area of reception of the sensor. The results of the tracked distances will be then plotted on screen.
Download Paper (PDF)

UB03.2

EXTRA-FUNCTIONAL PROPERTY SIMULATION WITH VIRTUAL PLATFORMS
Presenter:
Ralph Görgen, OFFIS - Intitute for Information Technology, DE
Authors:
Ralph Görgen, Kim Grüttner and Sören Schreiner, OFFIS - Intitute for Information Technology, DE
Abstract
The demo shows the usage of virtual platforms and model-based design to perform early analyses of extra-functional properties in a mixed-critical scenario. The application shown is a quadro-copter equipped with a camera system. The copter's flight controller is safety critical; the video processing is less critical. Both parts of the system are implemented in a single chip, a Xilinx ZNQ SoC. The video processing is implemented in the ARM dual-core, the flight controller is realized in the FPGA part and based on two MicroBlaze cores. This platform has been modeled as an OVP-based virtual platform, which is extended by more fine grain timing models as well as power models. Furthermore, it can be coupled with a model of the quadro-copter physics and environment realized in iXtronics CamelView. We will show how to use this setup to analyze timing, power, and temperature behavior of the system and the interference between the high- and low-critical parts with respect to these properties.
Download Paper (PDF)

UB03.3

ETEAK: ASYNCHRONOUS DATAFLOWS SYNTHESIS ONTO FPGAS USING THE ETEAK FRAMEWORK
Presenter:
Mahdi Jelodari Mamaghani, The University of Manchester, GB
Authors:
Mahdi Jelodari Mamaghani, Jim Garside and Steve Furber, The University of Manchester, GB
Abstract
We exploit eTeak (De-Elastisation [DATE'15] enabled) to synthesise asynchronous dataflow descriptions in Balsa into synchronous structure loadable onto FPGA. We will be also able to demonstrate the software realisation of the same architecture running on a laptop and let the audience compare the hardware vs. software concurrency. A brief experiment conducted in our recent study where a prime number generator (aka sieve of Eratosthenes) is implemented both in software using the CSP compiler and hardware using eTeak: On average the hardware implementation runs 90-120x faster than its software counterpart while the processor clock speed is almost the same as the hardware clock speed (1.2GHz). This allows us to plan ahead and exploit eTeak toward energy-efficient synthesis. According to EPSRC's research portpolio this work falls under the most growing research subject of "Energy Efficiency" which aims to achieve an energy reduction of 26-43% by exploiting ICT.
Download Paper (PDF)

UB03.4

LISA: ENABLING LAYERED INTEROPERABILITY FOR INTERNET OF THINGS THROUGH LISA
Presenter:
Behailu Shiferaw Negash, University of Turku, FI
Authors:
Behailu Shiferaw Negash¹, Amir-Mohammad Rahmani¹, Tomi Westerlund¹, Pasi Liljeberg¹ and Hannu Tenhunen²
¹University of Turku, FI; ²University of Turku, FI and Royal Institute of Technology (KTH), SE
Abstract
There is high expectation towards the changes that come with the implementation of the Internet of Things (IoT). However, this vision is limited by the heterogeneous nature of IoT devices. This led to vertical application silos that are incapable of working together. To ease this problem of heterogeneity, we have developed a lightweight interoperability framework, LISA, to hide variations in communication technology and data formats and provide a uniform API for programmers. LISA is inspired by Network on Terminal Architecture (NoTA), an open framework from Nokia Research Center. There are few frameworks for interoperability of IoT. However, these frameworks fail to address the resource limitations of the majority of IoT devices. To the best of our knowledge, LISA is the first framework designed for resource constrained devices. This demonstration shows LISA in action, helping heterogeneous devices interoperate through a gateway in the fog layer between the devices and the cloud.
Download Paper (PDF)

UB03.5

NEURODSP: A MULTI-PURPOSE ENERGY-OPTIMIZED ACCELERATOR FOR NEURAL NETWORKS
Presenter:
Jean-Marc PHILIPPE, CEA LIST, FR
Authors:
Jean-Marc PHILIPPE, Alexandre CARBON and Renaud SCHMIT, CEA LIST, FR
Abstract
Deep Neural Networks (e.g. Convolutional Neural Networks) is a promising approach to design smart machines for a wide range of application domains (automotive, home automation, industry, etc.). Due to their structure, these processing chains are compute intensive and difficult to embed into low power systems. To tackle this challenge, CEA LIST investigated the NeuroDSP hardware accelerator IP, able to be embedded into FPGA- or ASIC-based systems. Providing the system with a dramatic performance/watt ratio improvement, the IP can sustain 450GMACS/W in FDSOI 28nm technology, meeting the requirements of high-end embedded applications. The proposed demonstration features a comparison between three implementations of a CNN processing chain used to detect faces in a large image database. It shows that a single cluster FPGA-based implementation of the NeuroDSP IP at 100MHz is able to outperform both a Raspberry Pi 2 and an Odroid-XU3 board by a factor of respectively 10 and 6 in performance.
Download Paper (PDF)

UB03.6

IDDD: AN INTERACTIVE DEPENDABILITY DRIVEN DESIGN SPACE EXPLORATION
Presenter:
Stefan Scharoba, Brandenburg University of Technology Cottbus-Senftenberg, DE
Authors:
Stefan Scharoba, Jacob Lorenz and Heinrich T. Vierhaus, Brandenburg University of Technology Cottbus-Senftenberg, DE
Abstract
Due to the downscaling of transistor feature sizes, today's integrated circuits are much more likely to be affected by transient or permanent faults. In order to still meet certain dependability requirements, many different fault tolerance techniques have been developed, which can handle these faults in the field. Each of these techniques is associated with distinct costs and benefits. As a consequence, finding the fault tolerant implementation of the system that meets the actual requirements best represents a challenging task. We propose a tool that supports this process. It offers a set of hardware based fault tolerance techniques that can be applied to a given VHDL model. Afterwards, costs and benefits of the respective design choice are estimated automatically. Thus several fault tolerant versions of the design can be evaluated and compared with each other without implementing them manually. Finally, the VHDL code of the preferred design candidate can be generated by the tool.
Download Paper (PDF)

UB03.7

DIGITALLY DRIVEN TOP-DOWN METHODOLOGY FOR MIXED SIGNAL CIRCUIT DESIGN
Presenter:
Markus Mueller, University of Heidelberg, DE
Authors:
Markus Mueller, Maximilian Thuermer and Ulrich Bruening, University of Heidelberg, DE
Abstract
In this methodology,synthesizable modules and full custom blocks are first described in an HDL in a top-down approach. For analog cells, real number based models are created.Once the complete mixed signal model is done, each cell in the design is completely described concerning interface and behavior. The models then serve as specification for the full custom cell development.Schematics which don't include any primitives are automatically generated from the HDL description by a scripted flow to ensure consistency.Design space exploration can be done fast and very efficient this way. Cells which can be reused at different places in the design are identified and problems arising from interactions on the system level are found early in the design phase.This methodology accelerates the design process significantly, avoids errors and provides higher flexibility for design changes. A digital centric design example of a High Speed SerDes IP is demonstrated using the described methodology.
Download Paper (PDF)

UB03.8

GPCDS: AN INTERACTIVE TOOL FOR CREATING SCHEMATIC MODULE GENERATORS IN ANALOG IC DESIGN
Presenter:
Matthias Greif, Reutlingen University, DE
Authors:
Matthias Greif and Juergen Scheible, Reutlingen University, DE
Abstract
While digital design automation is highly developed, analog design automation still remains behind the demands. Previous approaches of circuit creation, which are usually based on optimization algorithms, do not satisfy industrial requirements. A promising alternative is given by procedural approaches, which imitate the solution strategy of a human expert. We are working on parameterized generators (such as PCells) for analog circuit and layout modules, special kinds of such procedures. We present "gPCDS", a novel tool for the creation of schematic generators for analog circuit design. Associated with a common design environment, gPCDS offers a sophisticated interactive design flow for the development of schematic PCells. gPCDS thus substitutes the crucial process of manual code writing by an intuitive graphic-based way of schematic PCell creation. The GUI of gPCDS provides a variety of useful functions, such as defining parameter ranges or placing predefined building blocks.
Download Paper (PDF)

UB03.9

PFPSIM: A PROGRAMMABLE FORWARDING PLANE SIMULATOR
Presenter:
Gordon Bailey, Concordia University, CA
Author:
Gordon Bailey, Concordia University, CA
Abstract
We demonstrate PFPSim, a host-compiled simulator for early validation and analysis of packet processing applications on programmable forwarding plane architectures, used in software defined networks. The simulation model is automatically generated from a high-level description of the hardware/software architecture of the forwarding device and the behavioral description of the various modules in the architecture. Our high-level architectural description language is capable of defining many-core network processors as well as reconfigurable pipelines. The behavior of the fixed-function processing elements in the architecture is defined in C++. The code targeted for the processor cores, or reconfigurable pipeline stages, is compiled from P4, an emerging programming language for packet processing applications. Network dataplane programmers can use PFPSim as a virtual prototype to simulate and debug their applications before hardware availability.
Download Paper (PDF)

UB03.10

ALPT: A FAST PROTOTYPING METHODOLOGY WITH CONSTRAINED FLOORPLANING ON ANALOG LAYOUT GENERATION
Presenter:
Po-Cheng Pan, National Chiao Tung University, TW
Authors:
Po-Cheng Pan, Hung-Wen Huang and Hung-Ming Chen, National Chiao Tung University, TW
Abstract
Layout generation in the recent analog design is challenging by its critical layout dependent effect (LDE). Based on the same netlist design, different layouts lead distinct performances. Therefore, it is necessary to observe and avoid the LDE during generation. Traditionally, the strategies of analog layout generation mostly count on experienced designers. However, the experience is based on time-consuming manually try-run, which is inefficient and unreliable. In this work, we develop a fast prototyping for analog layout generation. In our approach, we apply a fast floorplanning algorithm, for multi-layout generation and select the feasible results w.r.t. the analog constraints pre-decided. For practical usage, we implement this approach embedded on the EDA-tool so that layout designers are able to design with such prototypes for efficiency. The demonstration includes layout prototyping generation, the integration between our program and EDA-tool and the resulting layout prototypes.
Download Paper (PDF)

17:30

End of session

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