IP2 Interactive Presentations

Label	Presentation Title Authors
IP2-1	(Best Paper Award Candidate) ANALYZING THE IMPACT OF INJECTED SENSOR DATA ON AN ADVANCED DRIVER ASSISTANCE SYSTEM USING THE OP2TIMUS PROTOTYPING PLATFORM Speaker: Alexander Stühring, University of Oldenburg, DE Authors: Alexander Stühring¹, Günter Ehmen¹ and Sibylle Fröschle² ¹University of Oldenburg, DE; ²OFFIS Institute for Information Technology, DE Abstract Modern vehicles are running complex and safety critical applications distributed over several Electronic Control Units (ECUs). Some ECUs are equipped with communication interfaces providing access to other devices, networks or remote services. Since the number of attack vectors is increasing, an early investigation of the impact of attacks becomes steadily more important. This paper gives an example how manipulated sensor data injected to the CAN bus affects an Advanced Driver Assistance System (ADAS). Within multiple experiments we illustrate the impact of different aspects like the sending rate. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-2	HARDWARE TROJANS IN INCOMPLETELY SPECIFIED ON-CHIP BUS SYSTEMS Speaker: Nicole Fern, UC Santa Barbara, US Authors: Nicole Fern, Ismail San, Cetin Kaya Koc and Kwang-Ting (Tim) Cheng, UC Santa Barbara, US Abstract The security, functionality, and performance of the on-chip bus system is critical in an SoC design. We highlight the susceptibility of current bus implementations to Hardware Trojans hiding in unspecified functionality. Unlike existing Trojans which aim to disrupt normal bus behavior and are often designed for a specific protocol and topology, we present a general model for creating a covert Trojan communication channel between SoC components. From our channel model, which is applicable to any topology and protocol, one can create circuitry allowing information to flow covertly by altering existing bus signals only when they are unspecified. We give the specifics of this circuitry for AMBA AXI4 and APB, then create a system comprised of several master and slave units connected by an AXI4-Lite interconnect to quantify the overhead of the Trojan channel and illustrate the ability of our Trojans to evade a suite of protocol compliance checking assertions from ARM. We further outline several detection strategies for this class of hardware Trojan. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-3	WORKLOAD-AWARE POWER OPTIMIZATION STRATEGY FOR ASYMMETRIC MULTIPROCESSORS Speaker: Emanuele Del Sozzo, Politecnico di Milano, IT Authors: Emanuele Del Sozzo, Gianluca Durelli, Ettore Trainiti, Antonio Miele, Marco Domenico Santambrogio and Cristiana Bolchini, Politecnico di Milano, IT Abstract Asymmetric multi-core architectures, such as the ARM big.LITTLE, are emerging as successful solutions for the embedded and mobile markets due to their capabilities to trade-off performance and power consumption. However, both the HMP scheduler integrated in the commercial products and the previous research approaches are not able to fully exploit such potentiality. We propose a new runtime resource management policy for the big.LITTLE architecture integrated in Linux aimed at optimizing the power consumption while fulfilling performance requirements specified for the running applications. Experimental results show an improvement of the 11% on the performance and at the same time 8% in peak power consumption w.r.t. the current Linux HMP solution. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-4	(Best Paper Award Candidate) THE SLOWDOWN OR RACE-TO-IDLE QUESTION: WORKLOAD-AWARE ENERGY OPTIMIZATION OF SMT MULTICORE PLATFORMS UNDER PROCESS VARIATION Speaker: Anup Das, University of Southampton, GB Authors: Anup Das, Geoff Merrett and Bashir Al-Hashimi, University of Southampton, GB Abstract Increasing use of high performance applications on multicore platforms has proliferated energy consumption, transforming this as a primary design optimization objective. Two widely used approaches for reducing energy consumption in multithreaded workloads are slowdown (using DVFS) and race-to-idle. In this paper, we first demonstrate that most energy efficient choice is dependent on (1) workload (memory bound, CPU bound etc.), (2) process variation and (3) support for Simultaneous Multithreading (SMT). We then propose an approach for mapping application threads on SMT multicore systems at runtime, to minimize energy consumption. The proposed approach interfaces with the operating system and hardware performance counters and timers to characterize application threads. This characterization captures the effect of process variation on execution time and identifies the break-even operating point, where one strategy (slowdown or race-to-idle) outperforms the other. Thread mapping is performed using these characterized data by iteratively collapsing application threads (SMT) followed by binary programming-based thread mapping. Finally, performance slack is exploited at run-time to select between slowdown and race-to-idle, based upon the break-even operating point calculated for each individual thread. This end-to-end approach is implemented as a run-time manager for the Linux operating system and is validated across a range of high performance applications. Results demonstrate up to 13% energy reduction over all state-of-the-art approaches, with an average of 18% improvement over Linux. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-5	TOWARDS GENERAL PURPOSE COMPUTATIONS ON LOW-END MOBILE GPUS Speaker: Leonidas Kosmidis, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES Authors: Matina Maria Trompouki¹ and Leonidas Kosmidis² ¹Universitat Politècnica de Catalunya, ES; ²Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES Abstract GPUs traditionally offer high computational capabilities, frequently higher than their CPU counterparts. While high-end mobile GPUs vendors introduced recently general purpose APIs, such as OpenCL, to leverage their computational power, the vast majority of the mobile devices lack such support. Despite that their graphics APIs have similarities with desktop graphics APIs, they have significant differences, which prevent the use of well-known techniques that offer general-purpose computations over such interfaces. In this paper we show how these obstacles can be overcome, in order to achieve general purpose programmability of these devices. As a proof of concept we implemented our proposal on a real embedded platform (Raspberry Pi) based on Broadcom's VideoCore IV GPU, obtaining a speedup of 7.2X over the CPU. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-6	ESTIMATING DELAY DIFFERENCES OF ARBITER PUFS USING SILICON DATA Speaker: Keshab Parhi, University of Minnesota, US Authors: Satya Venkata Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris Kim and Keshab Parhi, University of Minnesota, US Abstract This paper presents a novel approach to estimate delay differences of each stage in a standard MUX-based physical unclonable function (PUF). Test data collected from PUFs fabricated using 32 nm process are used to train a linear model. The delay differences of the stages directly correspond to the model parameters. These parameters are trained by using a least mean square (LMS) adaptive algorithm. The accuracy of the response using the proposed model is around 97.5% and 99.5% for two different PUFs. Second, the PUF is also modeled by a perceptron. The perceptron has almost 100% classification accuracy. A comparison shows that the perceptron model parameters are scaled versions of the model derived by the LMS algorithm. Thus, the delay differences can be estimated from the perceptron model where the scaling factor is computed by comparing the models of the LMS algorithm and the perceptron. Because the delay differences are challenge independent, these parameters can be stored on the server. This will enable the server to issue random challenges whose responses need not be stored. An analysis of the proposed model confirms that the delay differences of all stages of the PUFs on the same chip belong to the same Gaussian probability density function. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-7	ON THE USE OF FORWARD BODY BIASING TO DECREASE THE REPEATABILITY OF LASER-INDUCED FAULTS Speaker: Marc Lacruche, Ecole Nationale Supérieure des Mines de Saint Etienne (ENSM-SE), FR Authors: Marc Lacruche¹, Noemie Beringuier-Boher¹, Jean-Max Dutertre¹, Jean-Baptiste Rigaud¹ and Edith Kussener² ¹Ecole Nationale Supérieure des Mines de Saint Etienne (ENSM-SE), FR; ²IM2NP, FR Abstract This paper presents a study on the effect of Forward Body Biasing on the laser fault sensitivity of a CMOS 90nm microcontroller. Tests were performed on a register of this target, under several supply voltage and body bias settings, showing significant laser sensitivity variations. Based on these results, a method which aims at decreasing fault repeatability by using variable supply voltage and body bias settings is proposed. Finally, tests are performed on an implementation of this method on a temporally redundant AES and the results are presented. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-8	SEQUENTIAL ANALYSIS DRIVEN RESET OPTIMIZATION TO IMPROVE POWER, AREA AND ROUTABILITY Speaker: Srihari Yechangunja, Mentor Graphics Corporation, IN Authors: Srihari Yechangunja¹, Raj Shekhar¹, Mohit Kumar¹, Nikhil Tripathi¹, Abhishek Ranjan¹, Abhishek Mittal¹, Jianfeng Liu², Minyoung Mo², Kyungtae Do², Jung Yun Choi² and SungHo Park² ¹Mentor Graphics Corporation, IN; ²S.LSI, Samsung Electronics Co. Ltd, KR Abstract Resets are required in the design to initialize the hardware for system operation and to force it into a known state for simulation or to recover from an error. Given the increasing design complexity and time-to-market pressures, figuring out the registers which do not require resets is extremely challenging. In this paper, we present a novel algorithm which uses observability based sequential analysis to identify the registers in design which do not require resets. With the proposed algorithm, we have seen that in some cases 70% registers in the design can have redundant resets. Further, with removal of the redundant resets on registers up to 22% sequential power savings and up to 3% area reduction post-layout can be obtained. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-9	EFFICIENT GLOBAL OPTIMIZATION OF MEMS BASED ON SURROGATE MODEL ASSISTED EVOLUTIONARY ALGORITHM Speaker: Bo Liu, Glyndwr University, GB Authors: Bo Liu¹ and Anna Nikolaeva² ¹Glyndwr University, GB; ²Bauman Moscow State Technical University, RU Abstract Optimization plays a key role in MEMS design. However, most MEMS design optimization (exploration) methods either depend on ad-hoc analytical / behavioural models or time consuming numerical simulations. Surrogate modeling techniques have been introduced to integrate generality and efficiency, but the number of design variables which can be handled by most existing efficient MEMS design optimization methods is often less than 5. To address the above challenges, a new method, called Adaptive Gaussian Process-Assisted Differential Evolution for MEMS Design Optimization (AGDEMO) is proposed. The key idea is the proposed ON-LINE adaptive surrogate model assisted optimization framework. In particular, AGDEMO performs global optimization of MEMS using numerical simulation and the differential evolution (DE) algorithm, and a Gaussian process surrogate model is constructed ON-LINE to predict the results of expensive numerical simulations. AGDEMO is tested by two actuators (both with 9 design variables). Comparisons with state-of-the-art methods verify advantages of AGDEMO in terms of efficiency, optimization capacity and scalability. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-10	EFFICIENT MONITORING OF LOOSE-ORDERING PROPERTIES FOR SYSTEMC TLM Speaker: Yuliia Romenska, Univ. Grenoble Alpes, VERIMAG, FR Authors: Yuliia Romenska¹ and Florence Maraninchi² ¹Univ. Grenoble Alpes, VERIMAG, FR; ²Grenoble INP & Verimag, FR Abstract SystemC Transaction-level modeling (TLM) provides high-level component-based models for SoCs, for which Assertion-Based-Verification (ABV) allows property checking early in the design cycle. We introduce the notion of loose-ordering to specify when components interact with each other and we propose a set of patterns to capture this notion in assertions. This new notion can already be expressed in languages like PSL, for which there exist tools to generate ABV monitors. But the definition of dedicated patterns makes it easier to write the properties. Moreover we define a direct translation of these patterns into SystemC monitors, and we show that it avoids the combinatorial explosion that would occur during a prior translation into PSL. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-11	TESTABLE DESIGN OF REPEATERLESS LOW SWING ON-CHIP INTERCONNECT Speaker: Naveen Kadayinti, Indian Institute of Technology Bombay, IN Authors: Naveen Kadayinti and Dinesh Sharma, Indian Institute of Technology Bombay, IN Abstract Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a weak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology. Download Paper (PDF; Only available from the DATE venue WiFi)
IP2-12	ALL-DIGITAL HYBRID-CONTROL BUCK CONVERTER FOR INTEGRATED VOLTAGE REGULATOR APPLICATIONS Speaker: Visvesh Sathe, University of Washington, US Authors: Ta-tung Yen, Bin Yu and Visvesh Sathe, University of Washington, US Abstract With efficiency and performance gains from subsequent CMOS technology generations continuing to taper-off, power-dissipation remains a roadblock to maintaining growth in computational performance. Power management systems are expected to continue to heavily rely on Dynamic Voltage and Frequency Scaling (DVFS), and Integrated Voltage Regulation (IVR) in particular, to drive improvements in energy-efficiency through finer supply-voltage control. As voltage domains continue to shrink, and multiple IVRs are employed within a System-on-Chip (SoC), all-digital buck converters will become increasingly important from a scalability, portability, and methodology-compatibility perspective. In addition to some of the existing challenges facing Voltage Regulator Modules (VRMs), IVR implementations are faced with additional efficiency and transient response due to the limited available filter capacitance. In this paper, we propose an alldigital hybrid-control buck converter which addresses these key challenges effectively by regulating supply voltage based on slack information from a critical path monitor, a novel and accurate technique for digital derivative measurement for effective PID control, and the use of digital non-linear control for fast transient response. Simulations in an industrial 65nm process technology demonstrate stable, energy-efficient operation with fast load regulation. Operating with a single phase, using package mounted inductor and filter capacitor models, the converter achieves a 25mV droop for a 5A load current ramp at 500mA/ns. With a high-side supply voltage of 2V, the converter achieves a peak efficiency of 86% at 2A. Download Paper (PDF; Only available from the DATE venue WiFi)

Label

Presentation Title
Authors

IP2-1

(Best Paper Award Candidate)
ANALYZING THE IMPACT OF INJECTED SENSOR DATA ON AN ADVANCED DRIVER ASSISTANCE SYSTEM USING THE OP2TIMUS PROTOTYPING PLATFORM
Speaker:
Alexander Stühring, University of Oldenburg, DE
Authors:
Alexander Stühring¹, Günter Ehmen¹ and Sibylle Fröschle²
¹University of Oldenburg, DE; ²OFFIS Institute for Information Technology, DE
Abstract
Modern vehicles are running complex and safety critical applications distributed over several Electronic Control Units (ECUs). Some ECUs are equipped with communication interfaces providing access to other devices, networks or remote services. Since the number of attack vectors is increasing, an early investigation of the impact of attacks becomes steadily more important. This paper gives an example how manipulated sensor data injected to the CAN bus affects an Advanced Driver Assistance System (ADAS). Within multiple experiments we illustrate the impact of different aspects like the sending rate.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-2

HARDWARE TROJANS IN INCOMPLETELY SPECIFIED ON-CHIP BUS SYSTEMS
Speaker:
Nicole Fern, UC Santa Barbara, US
Authors:
Nicole Fern, Ismail San, Cetin Kaya Koc and Kwang-Ting (Tim) Cheng, UC Santa Barbara, US
Abstract
The security, functionality, and performance of the on-chip bus system is critical in an SoC design. We highlight the susceptibility of current bus implementations to Hardware Trojans hiding in unspecified functionality. Unlike existing Trojans which aim to disrupt normal bus behavior and are often designed for a specific protocol and topology, we present a general model for creating a covert Trojan communication channel between SoC components. From our channel model, which is applicable to any topology and protocol, one can create circuitry allowing information to flow covertly by altering existing bus signals only when they are unspecified. We give the specifics of this circuitry for AMBA AXI4 and APB, then create a system comprised of several master and slave units connected by an AXI4-Lite interconnect to quantify the overhead of the Trojan channel and illustrate the ability of our Trojans to evade a suite of protocol compliance checking assertions from ARM. We further outline several detection strategies for this class of hardware Trojan.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-3

WORKLOAD-AWARE POWER OPTIMIZATION STRATEGY FOR ASYMMETRIC MULTIPROCESSORS
Speaker:
Emanuele Del Sozzo, Politecnico di Milano, IT
Authors:
Emanuele Del Sozzo, Gianluca Durelli, Ettore Trainiti, Antonio Miele, Marco Domenico Santambrogio and Cristiana Bolchini, Politecnico di Milano, IT
Abstract
Asymmetric multi-core architectures, such as the ARM big.LITTLE, are emerging as successful solutions for the embedded and mobile markets due to their capabilities to trade-off performance and power consumption. However, both the HMP scheduler integrated in the commercial products and the previous research approaches are not able to fully exploit such potentiality. We propose a new runtime resource management policy for the big.LITTLE architecture integrated in Linux aimed at optimizing the power consumption while fulfilling performance requirements specified for the running applications. Experimental results show an improvement of the 11% on the performance and at the same time 8% in peak power consumption w.r.t. the current Linux HMP solution.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-4

(Best Paper Award Candidate)
THE SLOWDOWN OR RACE-TO-IDLE QUESTION: WORKLOAD-AWARE ENERGY OPTIMIZATION OF SMT MULTICORE PLATFORMS UNDER PROCESS VARIATION
Speaker:
Anup Das, University of Southampton, GB
Authors:
Anup Das, Geoff Merrett and Bashir Al-Hashimi, University of Southampton, GB
Abstract
Increasing use of high performance applications on multicore platforms has proliferated energy consumption, transforming this as a primary design optimization objective. Two widely used approaches for reducing energy consumption in multithreaded workloads are slowdown (using DVFS) and race-to-idle. In this paper, we first demonstrate that most energy efficient choice is dependent on (1) workload (memory bound, CPU bound etc.), (2) process variation and (3) support for Simultaneous Multithreading (SMT). We then propose an approach for mapping application threads on SMT multicore systems at runtime, to minimize energy consumption. The proposed approach interfaces with the operating system and hardware performance counters and timers to characterize application threads. This characterization captures the effect of process variation on execution time and identifies the break-even operating point, where one strategy (slowdown or race-to-idle) outperforms the other. Thread mapping is performed using these characterized data by iteratively collapsing application threads (SMT) followed by binary programming-based thread mapping. Finally, performance slack is exploited at run-time to select between slowdown and race-to-idle, based upon the break-even operating point calculated for each individual thread. This end-to-end approach is implemented as a run-time manager for the Linux operating system and is validated across a range of high performance applications. Results demonstrate up to 13% energy reduction over all state-of-the-art approaches, with an average of 18% improvement over Linux.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-5

TOWARDS GENERAL PURPOSE COMPUTATIONS ON LOW-END MOBILE GPUS
Speaker:
Leonidas Kosmidis, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES
Authors:
Matina Maria Trompouki¹ and Leonidas Kosmidis²
¹Universitat Politècnica de Catalunya, ES; ²Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES
Abstract
GPUs traditionally offer high computational capabilities, frequently higher than their CPU counterparts. While high-end mobile GPUs vendors introduced recently general purpose APIs, such as OpenCL, to leverage their computational power, the vast majority of the mobile devices lack such support. Despite that their graphics APIs have similarities with desktop graphics APIs, they have significant differences, which prevent the use of well-known techniques that offer general-purpose computations over such interfaces. In this paper we show how these obstacles can be overcome, in order to achieve general purpose programmability of these devices. As a proof of concept we implemented our proposal on a real embedded platform (Raspberry Pi) based on Broadcom's VideoCore IV GPU, obtaining a speedup of 7.2X over the CPU.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-6

ESTIMATING DELAY DIFFERENCES OF ARBITER PUFS USING SILICON DATA
Speaker:
Keshab Parhi, University of Minnesota, US
Authors:
Satya Venkata Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris Kim and Keshab Parhi, University of Minnesota, US
Abstract
This paper presents a novel approach to estimate delay differences of each stage in a standard MUX-based physical unclonable function (PUF). Test data collected from PUFs fabricated using 32 nm process are used to train a linear model. The delay differences of the stages directly correspond to the model parameters. These parameters are trained by using a least mean square (LMS) adaptive algorithm. The accuracy of the response using the proposed model is around 97.5% and 99.5% for two different PUFs. Second, the PUF is also modeled by a perceptron. The perceptron has almost 100% classification accuracy. A comparison shows that the perceptron model parameters are scaled versions of the model derived by the LMS algorithm. Thus, the delay differences can be estimated from the perceptron model where the scaling factor is computed by comparing the models of the LMS algorithm and the perceptron. Because the delay differences are challenge independent, these parameters can be stored on the server. This will enable the server to issue random challenges whose responses need not be stored. An analysis of the proposed model confirms that the delay differences of all stages of the PUFs on the same chip belong to the same Gaussian probability density function.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-7

ON THE USE OF FORWARD BODY BIASING TO DECREASE THE REPEATABILITY OF LASER-INDUCED FAULTS
Speaker:
Marc Lacruche, Ecole Nationale Supérieure des Mines de Saint Etienne (ENSM-SE), FR
Authors:
Marc Lacruche¹, Noemie Beringuier-Boher¹, Jean-Max Dutertre¹, Jean-Baptiste Rigaud¹ and Edith Kussener²
¹Ecole Nationale Supérieure des Mines de Saint Etienne (ENSM-SE), FR; ²IM2NP, FR
Abstract
This paper presents a study on the effect of Forward Body Biasing on the laser fault sensitivity of a CMOS 90nm microcontroller. Tests were performed on a register of this target, under several supply voltage and body bias settings, showing significant laser sensitivity variations. Based on these results, a method which aims at decreasing fault repeatability by using variable supply voltage and body bias settings is proposed. Finally, tests are performed on an implementation of this method on a temporally redundant AES and the results are presented.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-8

SEQUENTIAL ANALYSIS DRIVEN RESET OPTIMIZATION TO IMPROVE POWER, AREA AND ROUTABILITY
Speaker:
Srihari Yechangunja, Mentor Graphics Corporation, IN
Authors:
Srihari Yechangunja¹, Raj Shekhar¹, Mohit Kumar¹, Nikhil Tripathi¹, Abhishek Ranjan¹, Abhishek Mittal¹, Jianfeng Liu², Minyoung Mo², Kyungtae Do², Jung Yun Choi² and SungHo Park²
¹Mentor Graphics Corporation, IN; ²S.LSI, Samsung Electronics Co. Ltd, KR
Abstract
Resets are required in the design to initialize the hardware for system operation and to force it into a known state for simulation or to recover from an error. Given the increasing design complexity and time-to-market pressures, figuring out the registers which do not require resets is extremely challenging. In this paper, we present a novel algorithm which uses observability based sequential analysis to identify the registers in design which do not require resets. With the proposed algorithm, we have seen that in some cases 70% registers in the design can have redundant resets. Further, with removal of the redundant resets on registers up to 22% sequential power savings and up to 3% area reduction post-layout can be obtained.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-9

EFFICIENT GLOBAL OPTIMIZATION OF MEMS BASED ON SURROGATE MODEL ASSISTED EVOLUTIONARY ALGORITHM
Speaker:
Bo Liu, Glyndwr University, GB
Authors:
Bo Liu¹ and Anna Nikolaeva²
¹Glyndwr University, GB; ²Bauman Moscow State Technical University, RU
Abstract
Optimization plays a key role in MEMS design. However, most MEMS design optimization (exploration) methods either depend on ad-hoc analytical / behavioural models or time consuming numerical simulations. Surrogate modeling techniques have been introduced to integrate generality and efficiency, but the number of design variables which can be handled by most existing efficient MEMS design optimization methods is often less than 5. To address the above challenges, a new method, called Adaptive Gaussian Process-Assisted Differential Evolution for MEMS Design Optimization (AGDEMO) is proposed. The key idea is the proposed ON-LINE adaptive surrogate model assisted optimization framework. In particular, AGDEMO performs global optimization of MEMS using numerical simulation and the differential evolution (DE) algorithm, and a Gaussian process surrogate model is constructed ON-LINE to predict the results of expensive numerical simulations. AGDEMO is tested by two actuators (both with 9 design variables). Comparisons with state-of-the-art methods verify advantages of AGDEMO in terms of efficiency, optimization capacity and scalability.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-10

EFFICIENT MONITORING OF LOOSE-ORDERING PROPERTIES FOR SYSTEMC TLM
Speaker:
Yuliia Romenska, Univ. Grenoble Alpes, VERIMAG, FR
Authors:
Yuliia Romenska¹ and Florence Maraninchi²
¹Univ. Grenoble Alpes, VERIMAG, FR; ²Grenoble INP & Verimag, FR
Abstract
SystemC Transaction-level modeling (TLM) provides high-level component-based models for SoCs, for which Assertion-Based-Verification (ABV) allows property checking early in the design cycle. We introduce the notion of loose-ordering to specify when components interact with each other and we propose a set of patterns to capture this notion in assertions. This new notion can already be expressed in languages like PSL, for which there exist tools to generate ABV monitors. But the definition of dedicated patterns makes it easier to write the properties. Moreover we define a direct translation of these patterns into SystemC monitors, and we show that it avoids the combinatorial explosion that would occur during a prior translation into PSL.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-11

TESTABLE DESIGN OF REPEATERLESS LOW SWING ON-CHIP INTERCONNECT
Speaker:
Naveen Kadayinti, Indian Institute of Technology Bombay, IN
Authors:
Naveen Kadayinti and Dinesh Sharma, Indian Institute of Technology Bombay, IN
Abstract
Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a weak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology.
Download Paper (PDF; Only available from the DATE venue WiFi)

IP2-12

ALL-DIGITAL HYBRID-CONTROL BUCK CONVERTER FOR INTEGRATED VOLTAGE REGULATOR APPLICATIONS
Speaker:
Visvesh Sathe, University of Washington, US
Authors:
Ta-tung Yen, Bin Yu and Visvesh Sathe, University of Washington, US
Abstract
With efficiency and performance gains from subsequent CMOS technology generations continuing to taper-off, power-dissipation remains a roadblock to maintaining growth in computational performance. Power management systems are expected to continue to heavily rely on Dynamic Voltage and Frequency Scaling (DVFS), and Integrated Voltage Regulation (IVR) in particular, to drive improvements in energy-efficiency through finer supply-voltage control. As voltage domains continue to shrink, and multiple IVRs are employed within a System-on-Chip (SoC), all-digital buck converters will become increasingly important from a scalability, portability, and methodology-compatibility perspective. In addition to some of the existing challenges facing Voltage Regulator Modules (VRMs), IVR implementations are faced with additional efficiency and transient response due to the limited available filter capacitance. In this paper, we propose an alldigital hybrid-control buck converter which addresses these key challenges effectively by regulating supply voltage based on slack information from a critical path monitor, a novel and accurate technique for digital derivative measurement for effective PID control, and the use of digital non-linear control for fast transient response. Simulations in an industrial 65nm process technology demonstrate stable, energy-efficient operation with fast load regulation. Operating with a single phase, using package mounted inductor and filter capacitor models, the converter achieves a 25mV droop for a 5A load current ramp at 500mA/ns. With a high-side supply voltage of 2V, the converter achieves a peak efficiency of 86% at 2A.
Download Paper (PDF; Only available from the DATE venue WiFi)

Visit us at DATE 2016