DATE 2014 Proceedings - Table of Contents

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Sessions: [Keynotes] [2.2] [2.3] [2.4] [2.5] [2.6] [2.7] [2.8] [3.2] [3.3] [3.4] [3.5] [3.6] [3.7] [3.8] [4.2] [4.3] [4.4] [4.5] [4.6] [4.7] [5.1] [5.2] [5.3] [5.4] [5.5] [5.6] [5.7] [5.8] [6.1] [6.2] [6.3] [6.4] [6.5] [6.6] [6.7] [7.0] [7.2] [7.3] [7.4] [7.5] [7.6] [7.7] [8.1] [8.2] [8.3] [8.4] [8.5] [8.6] [8.7] [8.8] [9.1] [9.2] [9.3] [9.4] [9.5] [9.6] [9.7] [9.8] [10.1] [10.2] [10.3] [10.4] [10.5] [10.6] [10.7] [11.0] [11.1] [11.2] [11.3] [11.4] [11.5] [11.6] [11.7] [11.8] [12.1] [12.2] [12.3] [12.4] [12.5] [12.6] [12.7] [12.8]

DATE 14 Sponsors
DATE Executive Committee
DATE Sponsors Committee
Technical Program Topic Chairs
Technical Program Committee
Reviewers
Foreword
Best Paper Awards
ACM SIGDA/EDAA PH.D. Forum
Call for Papers: DATE 2015

1.1.1 Keynote: System Design Challenges for Next Generation Wireless and Embedded Systems

Abstract icon PDF icon David Fuller - National Instruments, US


1.1.2 Keynote: The Growing Importance of Microelectronics from a Foundry Perspective

Abstract icon PDF icon Gerd Teepe - GLOBALFOUNDRIES, DE


2.2 Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads?

Organizer: Marco Casale-Rossi, Synopsys, Inc., US
Chair: Giovanni De Micheli, EPFL, CH

Abstract icon PDF icon Panelists: Rob Aitken, Antun Domic, Manfred Horstmann, Robert Hum, Philippe Magarshack

2.3 Making Automotive Systems Safer and More Energy Efficient

Chairs: Bart Vermeulen, NXP Semiconductors, NL; Martin Lukasiewycz, TUM CREATE, SG

Abstract icon PDF icon Emulation-Based Robustness Assessment for Automotive Smart-Power ICs
Manuel Harrant, Thomas Nirmaier, Jérôme Kirscher, Christoph Grimm, Georg Pelz
Abstract icon PDF icon Startup Error Detection and Containment to Improve the Robustness of Hybrid FlexRay Networks
Alexander Kordes, Bart Vermeulen, Abhijit Deb, Michael G. Wahl
Abstract icon PDF icon A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support
Jan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spägele, Michael Glaβ, Jürgen Teich
Abstract icon PDF icon Multi-Variant-based Design Space Exploration for Automotive Embedded Systems
Sebastian Graf, Michael Glaβ, Jürgen Teich, Christoph Lauer
Abstract icon PDF icon SAFE: Security-Aware FlexRay Scheduling Engine
Gang Han, Haibo Zeng, Yaping Li, Wenhua Dou
Abstract icon PDF icon Transient Errors Resiliency Analysis Technique for Automotive Safety Critical Applications
Sujan Pandey and Bart Vermeulen

2.4 Modern Challenges in Analog and Mixed-Signal Design

Chairs: Georges Gielen, KU Leuven, BE; Günhan Dündar, Bogazici University, TR

Abstract icon PDF icon Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures
Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
Abstract icon PDF icon Zonotope-based Nonlinear Model Order Reduction for Fast Performance Bound Analysis of Analog Circuits with Multiple-interval-valued Parameter Variations
Yang Song, Sai Manoj P.D., Hao Yu
Abstract icon PDF icon Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits
M. Velasco-Jiménez, R. Castro-López, E. Roca, F.V. Fernández
Abstract icon PDF icon Modeling of an Analog Recording System Design for ECoG and AP Signals
Nils Heidmann, Nico Hellwege, Tim Höhlein, Thomas Westphal, Dagmar Peters-Drolshagen, Steffen Paul
Abstract icon PDF icon Model Based Hierarchical Optimization Strategies for Analog Design Automation
Engin Afacan, Simge Ay, F.V. Fernández, Günhan Dündar, Faik Baskaya
Abstract icon PDF icon A Novel Low Power 11-bit Hybrid ADC Using Flash and Delay Line Architectures
Hsun-Cheng Lee and Jacob A. Abraham
Abstract icon PDF icon Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities
Carna Radojicic, Christoph Grimm, Javier Moreno, Xiao Pan
Abstract icon PDF icon Novel Circuit Topology Synthesis Method Using Circuit Feature Mining and Symbolic Comparison
Cristian Ferent and Alex Doboli
Abstract icon PDF icon An Embedded Offset and Gain Instrument for OpAmp IPs
Jinbo Wan and Hans G. Kerkhoff

2.5 Low-Power and Efficient Architectures

Chairs: Cristina Silvano, Politecnico di Milano, IT; Todd Austin, University of Michigan, US

Abstract icon PDF icon Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads
Seokwoo Song, Minseok Lee, John Kim, Woong Seo, Yeongon Cho, Soojung Ryu
Abstract icon PDF icon dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding
Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel
Abstract icon PDF icon Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements
Manu Komalan, José Ignacio Gómez Pérez, Christian Tenllado, Praveen Raghavan, Matthias Hartmann, Francky Catthoor
Abstract icon PDF icon EVX: Vector Execution on Low Power EDGE Cores
Milovan Duric, Oscar Palomar, Aaron Smith, Osman Unsal, Adrian Cristal, Mateo Valero, Doug Burger
Abstract icon PDF icon Program Affinity Performance Models for Performance and Utilization
Ryan W. Moore and Bruce R. Childers
Abstract icon PDF icon Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures
Matthias Boettcher, Bashir M. Al-Hashimi, Mbou Eyole, Giacomo Gabrielli, Alastair Reid
Abstract icon PDF icon A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters
Paolo Burgio, Robin Danilo, Andrea Marongiu, Philippe Coussy, Luca Benini

2.6 Real-Time Memory Hierarchies

Chairs: Benny Akesson, CTU Prague, CZ; Giuseppe Lipari, ENS - Cachan, FR

Abstract icon PDF icon On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis
Sebastian Altmeyer, Robert I. Davis
Abstract icon PDF icon WCET-Centric Dynamic Instruction Cache Locking
Huping Ding, Yun Liang, Tulika Mitra
Abstract icon PDF icon Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms
Chuansheng Dong, Haibo Zeng
Abstract icon PDF icon Time-predictable Execution of Multithreaded Applications on Multicore Systems
Ahmed Alhammad, Rodolfo Pellizzoni

2.7 Yield and Reliability for Robust Systems

Chairs: Joan Figueras, UPC, ES; Jose Pineda de Gyvez, NXP, NL

Abstract icon PDF icon Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales
Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Razi Seyyedi, Enrico Costenaro, Dan Alexandrescu
Abstract icon PDF icon Bias Temperature Instability Analysis of FinFET Based SRAM Cells
Seyab Khan, Innocent Agbo, Said Hamdioui, Halil Kukner, Ben Kaczer, Praveen Raghavan, Francky Catthoor
Abstract icon PDF icon SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis
Manish Rana, Ramon Canal
Abstract icon PDF icon INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis
Shrikanth Ganapathy, Ramon Canal, Dan Alexandrescu, Enrico Costenaro, Antonio González, Antonio Rubio
Abstract icon PDF icon Wear-out Analysis of Error Correction Techniques in Phase-change Memory
Caio Hoffman, Luiz Ramos, Rodolfo Azevedo, Guido Araújo
Abstract icon PDF icon Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation
Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri

2.8 Hot Topic: Technology Transfer towards Horizon 2020

Organizer: Rainer Leupers, RWTH Aachen, Germany
Chair: Norbert Wehn, TU Kaiserslautern, Germany

Abstract icon PDF icon Technology Transfer towards Horizon 2020
Rainer Leupers

3.2 Panel: The World Is Going... Analog & Mixed-Signal! What about EDA?

Organizer: Marco Casale-Rossi, Synopsys, Inc., US.
Chair: Pietro Palella, STMicroelectronics, IT

Abstract icon PDF icon Panelists: Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo

3.3 Secure Hardware Primitives and Implementations

Chairs: Paolo Maistri, TIMA, FR; Patrick Schaumont, Virginia Tech, US

Abstract icon PDF icon Lightweight Code-based Cryptography: QC-MDPC McEliece Encryption on Reconfigurable Devices
Ingo von Maurich, Tim Güneysu
Abstract icon PDF icon On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models
Patrick Haddad, Yannick Teglia, Florent Bernard, Viktor Fischer
Abstract icon PDF icon Clock-Modulation Based Watermark for Protection of Embedded Processors
Jedrzej Kufel, Peter Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough, James Myers

3.4 Modeling and Optimization of Power Distribution Networks

Chairs: Luca Daniel, MIT, US; Stefano Grivet-Talocia, Politecnico di Torino, IT

Abstract icon PDF icon Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications
A. Ubolli, S. Grivet-Talocia, M. Bandinu, A. Chinea
Abstract icon PDF icon Efficient Analysis of Variability Impact on Interconnect Lines and Resistor Networks
Jorge Fernández Villena, L. Miguel Silveira
Abstract icon PDF icon Implicit Index-aware Model Order Reduction for RLC/RC Networks
Nicodemus Banagaaya, Giuseppe Alì, Wil. H.A. Schilders, Caren Tischendorf
Abstract icon PDF icon P/G TSV Planning for IR-drop Reduction in 3D-ICs
Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori
Abstract icon PDF icon Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images
Jui-Hung Chien, Hao Yu, Ruei-Siang Hsu, Hsueh-Ju Lin, Shih-Chieh Chang
Abstract icon PDF icon Cost-Effective Decap Selection for Beyond Die Power Integrity
Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen
Abstract icon PDF icon Characterizing Power Delivery Systems with On/Off-Chip Voltage Regulators for Many-Core Processors
Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang
Abstract icon PDF icon Mask-Cost-Aware ECO Routing
Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang

3.5 Robust Architectures

Chairs: Todd Austin, University of Michigan, US; Muhammad Shafique, Karlsruhe Institute of Technology, DE

Abstract icon PDF icon Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems
Manil Dev Gomony, Benny Akesson, Kees Goossens
Abstract icon PDF icon Bus Designs for Time-Probabilistic Multicore Processors
Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla
Abstract icon PDF icon Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy
Ziyi Liu, Weidong Shi, Shouhuai Xu, Zhiqiang Lin
Abstract icon PDF icon Exploiting Narrow-Width Values for Improving Non-Volatile Cache Lifetime
Guangshan Duan, Shuai Wang
Abstract icon PDF icon Partial-SET: Write Speedup of PCM Main Memory
Bing Li, ShuChang Shan, Yu Hu, Xiaowei Li

3.6 Cyber Physical Systems: Security and Co-design

Chairs: Rolf Ernst, Technische Universitaet Braunschweig, DE; Anuradha Annaswamy, MIT, US

Abstract icon PDF icon Attack-Resilient Sensor Fusion
Radoslav Ivanov, Miroslav Pajic, Insup Lee
Abstract icon PDF icon Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees
Amir Aminifar, Enrico Bini, Petru Eles, Zebo Peng
Abstract icon PDF icon Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems
Matthias Kauer, Damoon Soudbakhsh, Dip Goswami, Samarjit Chakraborty, Anuradha M. Annaswamy
Abstract icon PDF icon Garbage Collection for Multi-version Index on Flash Memory
Kam-Yiu Lam, Jiantao Wang, Yuan-Hao Chang, Jen-Wei Hsieh, Po-Chun Huang, Chung Keung Poon, Chun Jiang Zhu
Abstract icon PDF icon D2Cyber: A Design Automation Tool for Dependable Cybercars
Arslan Munir, Farinaz Koushanfar
Abstract icon PDF icon Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems
Pierluigi Nuzzo, John B. Finn, Antonio Iannopollo, Alberto L. Sangiovanni-Vincentelli

3.7 On line Strategies for Reliability

Chairs: Fabrizio Lombardi, Northwestern University, US; JIe Han, University of Alberta, CA

Abstract icon PDF icon Spatial Pattern Prediction Based Management of Faulty Data Caches
Georgios Keramidas, Michail Mavropoulos, Anna Karvouniari, Dimitris Nikolos
Abstract icon PDF icon Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs
A. Das, A. Kumar, B. Veeravalli, C. Bolchini, A. Miele
Abstract icon PDF icon DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors
Hu Chen, Sanghamitra Roy, Koushik Chakraborty
Abstract icon PDF icon A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor
Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang

3.8 Hot Topic: Mission Profile Aware Design - The Solution for Successful Design of Tomorrows Automotive Electronics

Organizers: Goeran Jerke, Robert Bosch GmbH, DE; Oliver Bringmann, University of Tuebingen, DE
Chairs: Goeran Jerke, Robert Bosch GmbH, DE; Oliver Bringmann, University of Tuebingen, DE

Abstract icon PDF icon Mission Profile Aware IC Design - A Case Study
Goeran Jerke, Andrew B. Kahng
Abstract icon PDF icon Mission Profile Aware Robustness Assessment of Automotive Power Devices
Thomas Nirmaier, Andreas Burger, Manuel Harrant, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel, Georg Pelz
Abstract icon PDF icon Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design
C. Katzschke, M.-P. Sohn, M. Olbrich, V. Meyer zu Bexten, M. Tristl, E. Barke

4.2 Hot Topic: Multicore Systems in Safety Critical Electronic Control Units for Automotive and Avionics

Organizers and Chairs: Jürgen Becker, KIT, DE; Oliver Sander, KIT, DE

Abstract icon PDF icon Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems
Jan Nowotsch, Michael Paulitsch, Arne Henrichsen, Werner Pongratz, Andreas Schacht
Abstract icon PDF icon Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems
Oliver Sander, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Falco Bapp, Jürgen Becker, Hans Ulrich Michel, Dirk Kaule, Daniel Adam, Enno Lübbers, Jürgen Hairbucher, Andre Richter, Christian Herber, Andreas Herkersdorf

4.3 Secure Device Identification

Chairs: Tim Gueneysu, RUB, DE; Guido Bertoni, TMicroelectronics, IT

Abstract icon PDF icon ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design
Md. Tauhidur Rahman, Domenic Forte, Jim Fahrny, Mohammad Tehranipoor
Abstract icon PDF icon An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS
Mudit Bhargava, Ken Mai
Abstract icon PDF icon Increasing the Efficiency of Syndrome Coding for PUFs with Helper Data Compression
Matthias Hiller, Georg Sigl
Abstract icon PDF icon Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation
Jeroen Delvaux, Ingrid Verbauwhede

4.4 "Almost There" Emerging Technologies

Chairs: Ian O'Connor, University of Lyon, FR; Michael Niemier, University of Notre Dame, US

Abstract icon PDF icon IIR Filters Using Stochastic Arithmetic
Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel
Abstract icon PDF icon Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias
Alain Fourmigue, Giovanni Beltrame, Gabriela Nicolescu
Abstract icon PDF icon A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips
Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
Abstract icon PDF icon Fast and Accurate Computation Using Stochastic Circuits
Armin Alaghi, John P. Hayes

4.5 Memory System Architectures

Chairs: Muhammad Shafique, Karlsruhe Institute of Technology, DE; Cristina Silvano, Politecnico di Milano, IT

Abstract icon PDF icon Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests
Tianyue Lu, Licheng Chen, Mingyu Chen
Abstract icon PDF icon ALLARM: Optimizing Sparse Directories for Thread-Local Data
Amitabha Roy, Timothy M. Jones
Abstract icon PDF icon Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control
Biswabandan Panda, Shankar Balachandran
Abstract icon PDF icon A Multi Banked - Multi Ported - non Blocking Shared L2 Cache for MPSoC Platforms
Igor Loi, Luca Benini
Abstract icon PDF icon DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy
Zoran Jaksić, Ramon Canal
Abstract icon PDF icon Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD3)
Alen Bardizbanyan, Magnus Själander, David Whalley, Per Larsson-Edefors
Abstract icon PDF icon Distributed Cooperative Shared Last-Level Caching in Tiled Multiprocessor System on Chip
Preethi P. Damodaran, Stefan Wallentowitz, Andreas Herkersdorf

4.6 Code Generation and Optimization for Embedded Platforms

Chairs: Heiko Falk, Ulm University, DE; Florence Maraninchi, Grenoble IMP/VERIMAG, FR

Abstract icon PDF icon EATBit: Effective Automated Test for Binary Translation with High Code Coverage
Hui Guo, Zhenjiang Wang, Chenggang Wu, Ruining He
Abstract icon PDF icon On-Device Objective-C Application Optimization Framework for High-Performance Mobile Processors
Garo Bournoutian, Alex Orailoglu
Abstract icon PDF icon Code Generation for Embedded Heterogeneous Architectures on Android
Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich
Abstract icon PDF icon Design of Safety Critical Systems by Refinement
Alex Iliasov, Arseniy Alekseyev, Danil Sokolov, Andrey Mokhov
Abstract icon PDF icon Energy Optimization in Android Applications through Wakelock Placement
Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan
Abstract icon PDF icon A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems
Qingan Li, Yanxiang He, Yong Chen, Chun Jason Xue, Nan Jiang, Chao Xu
Abstract icon PDF icon Lifetime Holes Aware Register Allocation for Clustered VLIW Processors
Xuemeng Zhang, Hui Wu, Haiyan Sun, Jingling Xue

4.7 Dependable System Design

Chairs: Yiorgos Makris, University of Texas at Dallas, US; Michael Nicolaidis, TIMA, FR

Abstract icon PDF icon Real-Time Trust Evaluation in Integrated Circuits
Yier Jin, Dean Sullivan
Abstract icon PDF icon Verification-guided Voter Minimization in Triple-Modular Redundant Circuits
Dmitry Burlyaev, Pascal Fradet, Alain Girault
Abstract icon PDF icon Trade-offs in Execution Signature Compression for Reliable Processor Systems
Jonah Caplan, Maria Isabel Mera, Peter Milder, Brett H. Meyer
Abstract icon PDF icon An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems
Yue Gao, Sandeep K. Gupta, Yanzhi Wang, Massoud Pedram
Abstract icon PDF icon A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery
Cong Liu, Jie Han, Fabrizio Lombardi

5.1 Hot Topic: Predictable Multi-Core Computing

Organizer: Jürgen Teich, Erlangen-Nuremberg U, DE
Chairs: Petru Eles, Linkoping U, SE; Jürgen Teich, Erlangen-Nuremberg U, DE

Abstract icon PDF icon Impact of Resource Sharing on Performance and Performance Prediction
Jan Reineke, Reinhard Wilhelm
Abstract icon PDF icon Time-Critical Computing on a Single Chip Massively Parallel Processor
Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager
Abstract icon PDF icon Mapping Mixed-Criticality Applications on Multi-Core Architectures
Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele

5.2 Hot Topic: Hacking and Protecting Hardware: Threats and Challenges

Organizers: Said Hamdioui, TU Delft, NL; Giorgio Di Natale, LIRMM, FR
Chairs: Said Hamdioui, TU Delft, NL; Giorgio Di Natale, LIRMM, FR

Abstract icon PDF icon Hacking and Protecting IC Hardware
Said Hamdioui, Giorgio Di Natale, Gerard van Battum, Jean-Luc Danger, Fethulah Smailbegovic, Mark Tehranipoor

5.3 Reliable Systems in the Age of Variability

Chairs: Antonio Miele, Politecnico di Milano, IT; José L. Ayala, Complutense University of Madrid, ES

Abstract icon PDF icon Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs
Abbas Rahimi, Luca Benini, Rajesh K. Gupta
Abstract icon PDF icon Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W
Waleed Dweik, Murali Annavaram, Michel Dubois
Abstract icon PDF icon Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia MPSoCs
Anup Das, Akash Kumar, Bharadwaj Veeravalli
Abstract icon PDF icon Recovery-Based Resilient Latency-Insensitive Systems
Yuankai Chen, Xuan Zeng, Hai Zhou
Abstract icon PDF icon A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices
Pietro Mercati, Andrea Bartolini, Francesco Paterna, Tajana Simunic Rosing, Luca Benini
Abstract icon PDF icon Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits
Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang
Abstract icon PDF icon Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities
Semeen Rehman, Florian Kriebel, Muhammad Shafique, Jörg Henkel

5.4 Prediction and Optimization of Timing Variations

Chairs: Antonio Rubio, UPC Barcelona, ES; Marisa López Vallejo, UPM Madrid,ES

Abstract icon PDF icon Efficient High-Sigma Yield Analysis for High Dimensional Problems
Moning Zhang, Zuochang Ye, Yan Wang
Abstract icon PDF icon Sub-threshold Logic Circuit Design Using Feedback Equalization
Mahmoud Zangeneh, Ajay Joshi
Abstract icon PDF icon Stochastic Analysis of Bubble Razor
Guowei Zhang, Peter Beerel
Abstract icon PDF icon Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles
Yanzhi Wang, Xue Lin, Qing Xie, Naehyuck Chang, Massoud Pedram
Abstract icon PDF icon Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits
Mehrzad Nejat, Bijan Alizadeh, Ali Afzali Kusha
Abstract icon PDF icon A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance
Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan, Zhen Li

5.5 Boosting the Scalability of Formal Verification Technologies

Chairs: Fahim Rahim, Atrenta, FR; Bernd Becker, University of Freiburg, DE

Abstract icon PDF icon Scalable Liveness Verification for Communication Fabrics
Sebastiaan J.C. Joosten, Julien Schmaltz
Abstract icon PDF icon Property Directed Invariant Refinement for Program Verification
Tobias Welp, Andreas Kuehlmann
Abstract icon PDF icon Simple Interpolants for Linear Arithmetic
Christoph Scholl, Florian Pigorsch, Stefan Disch, Ernst Althaus
Abstract icon PDF icon Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization
G. Cabodi, P. Pasini, S. Quer, D. Vendraminetto
Abstract icon PDF icon Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic
Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl

5.6 Emerging Logic Technologies

Chairs: Mehdi Tahoori, KIT, DE; Marco Ottavi, University of Rome "Tor Vergata", IT

Abstract icon PDF icon RETLab: A Fast Design-automation Framework for Arbitrary RET Networks
Mohammad D. Mottaghi, Arjun Rallapalli, Chris Dwyer
Abstract icon PDF icon Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study
Robert Perricone, X. Sharon Hu, Joseph Nahas, Michael Niemier
Abstract icon PDF icon Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling
Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Deming Chen
Abstract icon PDF icon Rewiring for Threshold Logic Circuit Minimization
Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang
Abstract icon PDF icon Width Minimization in the Single-Electron Transistor Array Synthesis
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan
Abstract icon PDF icon Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints
Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
Abstract icon PDF icon Software-based Pauli Tracking in Fault-tolerant Quantum Circuits
Alexandru Paler, Simon Devitt, Kae Nemoto, Ilia Polian

5.7 Test generation and optimization

Chairs: Xiaoqing Wen, Kyushu Institute of Technology, JP; Grzegorz Mrugalski, Mentor Graphics, PL

Abstract icon PDF icon Efficient SMT-based ATPG for Interconnect Open Defects
Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker
Abstract icon PDF icon Interconnect Test for 3D Stacked Memory-on-Logic
Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen
Abstract icon PDF icon An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults
Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker
Abstract icon PDF icon Multi-Site Test Optimization for Multi-Vdd SoCs Using Space- and Time-Division Multiplexing
Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin Parekhji, Arvind Jain
Abstract icon PDF icon An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs
Nima Aghaee, Zebo Peng, Petru Eles
Abstract icon PDF icon Test and Non-Test Cubes for Diagnostic Test Generation Based on Merging of Test Cubes
Irith Pomeranz
Abstract icon PDF icon New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy
H. Ayari, F. Azais, S. Bernard, M. Comte, V. Kerzerho, M. Renovell

5.8 System Integration - The Bridge between More than Moore and More Moore

Organizers: Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE; Kai Hahn, University Siegen,DE
Chairs: Manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE; Kai Hahn, University Siegen, DE

Abstract icon PDF icon System Integration - The Bridge between More than Moore and More Moore
Andy Heinig, Manfred Dietrich, Andreas Herkersdorf, Felix Miller, Thomas Wild, Kai Hahn, Armin Grünewald, Rainer Brück, Steffen Kröhnert, Jochen Reisinger

6.1 Hot Topic: The Fight against Dark Silicon

Organizer: Jörg Henkel, Karlsruhe Institute of Technology, DE
Chairs: Jörg Henkel, Karlsruhe Institute of Technology, DE Jürgen Teich, Erlangen-Nuremberg U, DE

Abstract icon PDF icon A Landscape of the New Dark Silicon Design Regime
Michael B. Taylor
Abstract icon PDF icon Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs
Mohamed M. Sabry, Arvind Sridhar, David Atienza, Patrick Ruch, Bruno Michel
Abstract icon PDF icon Effective Resource Management towards Efficient Computing
Per Stenström

6.2 Embedded Tutorial: Emerging Transistor Technologies: From Devices to Architectures

Organizers: Michael Niemier, University of Notre Dame, US; X. Sharon Hu, University of Notre Dame, US
Chair: Michael Niemier, University of Notre Dame, US

Abstract icon PDF icon Modeling Steep Slope Devices: From Circuits to Architectures
Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, Jack Sampson, Vijaykrishnan Narayanan
Abstract icon PDF icon Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study
Indranil Palit, Behnam Sedighi, András Hortváth, X. Sharon Hu, Joseph Nahas, Michael Niemier

6.3 Management of Micro/Macro Renewable Energy Storage Systems

Chairs: Geoff Merrett, University of Southampton,UK Davide Brunelli, University of Trento, IT

Abstract icon PDF icon Asynchronous Design for New On-Chip Wide Dynamic Range Power Electronics
Delong Shang, Xuefu Zhang, Fei Xia, Alex Yakovlev
Abstract icon PDF icon Real-time Optimization of the Battery Banks Lifetime in Hybrid Residential Electrical Systems
Maurizio Rossi, Alessandro Toppano, Davide Brunelli
Abstract icon PDF icon Optimal Dimensioning of Active Cell Balancing Architectures
Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz, Matthias Kauer, Samarjit Chakraborty
Abstract icon PDF icon Optimal Design and Management of a Smart Residential PV and Energy Storage System
Di Zhu, Yanzhi Wang, Naehyuck Chang, Massoud Pedram
Abstract icon PDF icon Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting
Enrico Macrelli, Ningning Wang, Saibal Roy, Michael Hayes, Rudi Paolo Paganelli, Marco Tartagni, Aldo Romani
Abstract icon PDF icon Providing Regulation Services and Managing Data Center Peak Power Budgets
Baris Aksanli, Tajana Rosing
Abstract icon PDF icon The Energy Benefit of Level-crossing Sampling Including the Actuator's Energy Consumption
Burkhard Hensel, Klaus Kabitzsch

6.4 Power Delivery and Distribution

Chairs: Edith Beigné, CEA LETI Grenoble, FR; Domenik Helms, OFFIS Oldenburg, DE

Abstract icon PDF icon Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors
Masaaki Kondo, Hiroaki Kobyashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura
Abstract icon PDF icon SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing
Xin He, Guihai Yan, Yinhe Han, Xiaowei Li
Abstract icon PDF icon Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads
Samantak Gangopadhyay, Youngtak Lee, Saad Bin Nasir, Arijit Raychowdhury

6.5 Beyond EDA: Extending the Application Domain of Formal Methods

Chair: Christoph Scholl, University of Freiburg, DE; Gianpiero Cabodi, Politecnico di Torino, IT

Abstract icon PDF icon Using MaxBMC for Pareto-Optimal Circuit Initialization
Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
Abstract icon PDF icon Partial Witnesses from Preprocessed Quantified Boolean Formulas
Martina Seidl, Robert Könighofer
Abstract icon PDF icon Equivalence Checking for Function Pipelining in Behavioral Synthesis
Kecheng Hao, Sandip Ray, Fei Xie
Abstract icon PDF icon Towards the Formal Analysis of Microresonators Based Photonic Systems
Umair Siddique, Sofiène Tahar
Abstract icon PDF icon SKETCHILOG: Sketching Combinational Circuits
Andrew Becker, David Novo, Paolo Ienne
Abstract icon PDF icon Towards Verifying Determinism of SystemC Designs
Hoang M. Le, Rolf Drechsler

6.6 Model-Based Design and Hardware/Software Interfaces

Chairs: Wang Wang Yi, Uppsala University, SE; Oliver Bringmann, University of Tübingen, DE

Abstract icon PDF icon Library-Based Scalable Refinement Checking for Contract-Based Design
Antonio Iannopollo, Pierluigi Nuzzo, Stavros Tripakis, Alberto Sangiovanni-Vincentelli
Abstract icon PDF icon Isochronous Networks by Construction
Yu Bai, Klaus Schneider
Abstract icon PDF icon Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters
Paolo Burgio, Giuseppe Tagliavini, Francesco Conti, Andrea Marongiu, Luca Benini
Abstract icon PDF icon p-OFTL: An Object-based Semantic-aware Parallel Flash Translation Layer
Wei Wang, Youyou Lu, Jiwu Shu
Abstract icon PDF icon Using Guided Local Search for Adaptive Resource Reservation in Large-scale Embedded Systems
Timon D. ter Braak
Abstract icon PDF icon Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation
Eunhyek Park, Sungjoo Yoo, Sunggu Lee, Helen Li

6.7 Hardening Approaches at Different Design Levels

Chairs: Lorena Anghel, TIMA, FR; Jaume Abella, BSC, ES

Abstract icon PDF icon Nostradamus: Low-Cost Hardware-Only Error Detection for Processor Cores
Ralph Nathan, Daniel J. Sorin
Abstract icon PDF icon Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications
B. Alorda, C. Carmona, S. Bota
Abstract icon PDF icon A High Performance SEU-Tolerant Latch for Nanoscale CMOS Technology
Zhengfeng Huang
Abstract icon PDF icon A Low-Cost Radiation Hardened Flip-flop
Yang Lin, Mark Zwolinski, Basel Halak
Abstract icon PDF icon PSP-Cache: A Low-Cost Fault-Tolerant Cache Memory Architecture
Hamed Farbeh, Seyed Ghassem Miremadi
Abstract icon PDF icon A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction
Pilin Junsangsri, Fabrizio Lombardi, Jie Han

7.0 Special Day Keynote

Abstract icon PDF icon The Connected Car and Its Implication to the Automotive Chip Roadmap
Michael Bolle, Robert Bosch GmbH, DE

7.2 Embedded Tutorial: Cross Layer Resiliency in Real World

Organizer: Vikas Chandra, ARM, US
Chairs: Yanjing Li, Intel, US; Ulf Schlichtmann, TUM, DE

Abstract icon PDF icon Cross Layer Resiliency in Real World
Vikas Chandra

7.3 Low Power Methods and Multicore Architectures for Mobile Health Applications

Chairs: Ashoka Sathanur, Philips, NL; Giovanni Ansaloni, EPFL, CH

Abstract icon PDF icon Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes
Rubén Braojos, Ahmed Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza
Abstract icon PDF icon Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors
Daniele Bortolotti, Andrea Bartolini, Christian Weis, Davide Rossi, Luca Benini
Abstract icon PDF icon Context Aware Power Management for Motion-sensing Body Area Network Nodes
Filippo Casamassima, Elisabetta Farella, Luca Benini
Abstract icon PDF icon A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability
Georgios Karakonstantis, Aviinaash Sankaranarayanan, Mohamed M. Sabry, David Atienza, Andreas Burg
Abstract icon PDF icon Battery Aware Stochastic QoS Boosting in Mobile Computing Devices
Hao Shen, Qiuwen Chen, Qinru Qiu

7.4 Runtime Memory Optimization and GPU/Manycore Architectures

Chairs: Alberto Nannarelli, DTU Copenhagen, DK; Alberto Macii, PoliTo Torino, IT

Abstract icon PDF icon Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization
Karthik Chandrasekar, Sven Goossens, Christian Weis, Martijn Koedam, Benny Akesson, Norbert Wehn, Kees Goossens
Abstract icon PDF icon Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache
Haroon Mahmood, Massimo Poncino, Enrico Macii
Abstract icon PDF icon On GPU Bus Power Reduction with 3D IC Technologies
Young-Joon Lee and Sung Kyu Lim
Abstract icon PDF icon Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking
Paula Aguilera, Jungseob Lee, Amin Farmahini-Farahani, Katherine Morrow, Michael Schulte, Nam Sung Kim
Abstract icon PDF icon A Thermal Resilient Integration of Many-core Microprocessors and Main Memory by 2.5D TSI I/Os
Sih-Sian Wu, Kanwen Wang, Sai Manoj P. D., Tsung-Yi Ho, Mingbin Yu, Hao Yu
Abstract icon PDF icon Leveraging On-Chip Networks for Efficient Prediction on Multicore Coherence
Libo Huang
Abstract icon PDF icon An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems
Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi

7.5 Emerging Memory Technologies

Chairs: Aida Todri, CNRS .FR; Lars Bauer, KIT, DE

Abstract icon PDF icon Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM
Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi B. Tahoori
Abstract icon PDF icon Write-Once-Memory-Code Phase Change Memory
Jiayin Li, Kartik Mohanram
Abstract icon PDF icon Improving STT-MRAM Density through Multibit Error Correction
Brandon Del Bel, Jongyeon Kim, Chris H. Kim, Sachin S. Sapatnekar
Abstract icon PDF icon Energy Efficient In-Memory AES Encryption Based on Nonvolatile Domain-wall Nanowire
Yuhao Wang, Hao Yu, Dennis Sylvester, Pingfan Kong
Abstract icon PDF icon ICE: Inline Calibration for Memristor Crossbar-based Computing Engine
Boxun Li, Yu Wang, Yiran Chen, Hai (Helen) Li, Huazhong Yang
Abstract icon PDF icon Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication
Yuanfan Yang, Jimson Mathew, Dhiraj K Pradhan, Marco Ottavi, Salvatore Pontarelli

7.6 Performance and Timing Analysis

Chairs: Wang Wang Yi, Uppsala University, SE Petru Petru Eles, Linköping University, SE

Abstract icon PDF icon Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces
Sofiane Lagraa, Alexandre Termier, Frédéric Pétrot
Abstract icon PDF icon Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems
Neil Dhruva, Pratyush Kumar, Georgia Giannopoulou, Lothar Thiele
Abstract icon PDF icon Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints
Di Liu, Jelena Spasic, Jiali Teddy Zhai, Todor Stefanov, Gang Chen
Abstract icon PDF icon A Layered Approach for Testing Timing in the Model-Based Implementation
BaekGyu Kim, Hyeon I Hwang, Taejoon Park, Sang H. Son, Insup Lee
Abstract icon PDF icon Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP
Kenneth Balck, Olga Grinchtein, Justin Pearson
Abstract icon PDF icon Time-Decoupled Parallel SystemC Simulation
Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto
Abstract icon PDF icon A Unified Methodology for a Fast Benchmarking of Parallel Architecture
Alexandre Guerre, Jean-Thomas Acquaviva, Yves Lhuillier

7.7 Design-for-Test and Test Access

Chairs: Erik Jan Marinissen, IMEC, BE; Hans-Joachim Wunderlich, Univ. of Stuttgart, DE

Abstract icon PDF icon Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test
Michael E. Imhof, Hans-Joachim Wunderlich
Abstract icon PDF icon Testing PUF-Based Secure Key Storage Circuits
Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale
Abstract icon PDF icon Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network
Adam Zygmontowicz, Jennifer Dworak, Al Crouch, John Potter
Abstract icon PDF icon Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement
Andrew B. Kahng, Ilgweon Kang

8.1 System Simulation and Virtual Prototyping

Organizer: Johannes Stahl, Synopsys, US; Chair: Johannes Stahl, Synopsys, US

Abstract icon PDF icon Power Modeling and Analysis in Early Design Phases
Bernhard Fischer, Christian Cech, Hannes Muhr
Abstract icon PDF icon System-level Design Methodology Enabling Fast Development of Baseband MP-SoC for 4G Small Cell Base Station
Shan Tang, Ziyuan Zhu, Yongtao Su
Abstract icon PDF icon Virtual Prototype Life Cycle in Automotive Applications
Manfred Thanner

8.2 Hot Topic: Near Threshold Computing (NTC)

Organizer: Michael Huebner, Ruhr-University Bochum, DE
Chair: Michael Huebner, Ruhr-University Bochum, DE

Abstract icon PDF icon Extreme-Scale Computer Architecture: Energy Efficiency from the Ground up
Josep Torrellas
Abstract icon PDF icon Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon
Cristina Silvano, Gianluca Palermo, Sotirios Xydis, Ioannis Stamelakos
Abstract icon PDF icon Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing
Tobias Gemmeke, Mohamed M. Sabry, Jan Stuijt, Praveen Raghavan, Francky Catthoor, David Atienza

8.3 Physical Attacks and Countermeasures

Chairs: Francesco Regazzoni, Alari, CH ;Shivam Bhasin, Telecom Paristech, FR

Abstract icon PDF icon Efficiency of a Glitch Detector against Electromagnetic Fault Injection
Loic Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, Ludovic Guillaume-Sage, Jessy Clediere, Assia Tria
Abstract icon PDF icon Analyzing and Eliminating the Causes of Fault Sensitivity Analysis
Nahid Farhady Ghalaty, Aydin Aysu, Patrick Schaumont
Abstract icon PDF icon A Smaller and Faster Variant of RSM
Noritaka Yamashita, Kazuhiko Minematsu, Toshihiko Okamura, Yukiyasu Tsunoo
Abstract icon PDF icon A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks
Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle

8.4 Efficient Designs for Telecom and Financial Applications

Chair: Sergio Saponara, University of Pisa, IT; Amer Baghdadi, Telecom Bretagne, FR

Abstract icon PDF icon Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations
David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor
Abstract icon PDF icon Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL
Valentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton
Abstract icon PDF icon Hardware Implementation of a Reed-Solomon Soft Decoder Based on Information Set Decoding
Stefan Scholl, Norbert Wehn
Abstract icon PDF icon Ambient Variation-tolerant and Inter Components Aware Thermal Management for Mobile System on Chips
Francesco Paterna, Joe Zanotelli, Tajana Simunic Rosing
Abstract icon PDF icon Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition
Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor
Abstract icon PDF icon Mode-Controlled Dataflow Based Modeling & Analysis of a 4G-LTE Receiver
Hrishikesh Salunkhe, Orlando Moreira, Kees van Berkel

8.5 Modeling & Specification

Chairs: Wolfgang Mueller, University of Paderborn, DE; Francois PECHEUX, UPMC, FR

Abstract icon PDF icon An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations
Shu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay
Abstract icon PDF icon Automatic Specification Granularity Tuning for Design Space Exploration
Jiaxing Zhang, Gunar Schirner
Abstract icon PDF icon EDT: A Specification Notation for Reactive Systems
R. Venkatesh, Ulka Shrotri, G. Murali Krishna, Supriya Agrawal
Abstract icon PDF icon Model-Based Actor Multiplexing with Application to Complex Communication Protocols
Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich
Abstract icon PDF icon A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving
Alexander Biewer, Jens Gladigau, Christian Haubelt
Abstract icon PDF icon DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling
Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano

8.6 Mapping and Scheduling for Many-Core Embedded Systems

Chairs: Marc Geilen, Eindhoven University of Technology, NL; Sébastien Le Beux, Ecole Centrale de Lyon, FR

Abstract icon PDF icon Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing
Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel
Abstract icon PDF icon GPU-EvR: Run-time Event Based Real-time Scheduling Framework on GPGPU Platform
Haeseung Lee, Mohammad Abdullah Al Faruque
Abstract icon PDF icon Multi-Objective Distributed Run-time Resource Management for Many-Cores
Stefan Wildermann, Michael Glaβ, Jürgen Teich
Abstract icon PDF icon CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel
Andrew Nelson, Ashkan Beyranvand Nejad, Anca Molnos, Martijn Koedam, Kees Goossens
Abstract icon PDF icon Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor
Myungsun Kim, Kibeom Kim, James R. Geraci, Seongsoo Hong
Abstract icon PDF icon hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding
Daniel Palomino, Muhammad Shafique, Hussam Amrouch, Altamiro Susin, Jörg Henkel
Abstract icon PDF icon Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions
Mehdi Kamal, Amin Ghasemazar, Ali Afzali-Kusha, Massoud Pedram

8.7 Performance Modeling and Delay Test

Chairs: Robert Aitken, ARM, US Mehdi Tahoori, KIT, DE

Abstract icon PDF icon Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation
Li Yu, Sharad Saxena, Christopher Hess, Ibrahim (Abe) M. Elfadel, Dimitri Antoniadis, Duane Boning
Abstract icon PDF icon Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction
Shuangyue Zhang, Fan Lin, Chun-Kai Hsu, Kwang-Ting Cheng, Hong Wang
Abstract icon PDF icon Substituting Transition Faults with Path Delay Faults as a Basic Delay Fault Model
Irith Pomeranz
Abstract icon PDF icon Standard Cell Library Tuning for Variability Tolerant Designs
Sebastien Fabrie, Juan Diego Echeverri, Maarten Vertregt, José Pineda de Gyvez
Abstract icon PDF icon Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations
André Lange, Christoph Sohrmann, Roland Jancke, Joachim Haase, Ingolf Lorenz, Ulf Schlichtmann

8.8 Hot Topic: Beyond CMOS Ultra-low-power Computing

Organizer: Saibal Mukhopadhyay, Georgia Institute of Technology, US
Chairs: Arijit Raychowdhury, Georgia Institute of Technology, US; Saibal Mukhopadhyay, Georgia Institute of Technology, US

Abstract icon PDF icon Ultra-low Power Electronics with Si/Ge Tunnel FET
Amit Ranjan Trivedi, Mohammad Faisal Amir, Saibal Mukhopadhyay
Abstract icon PDF icon Brain-Inspired Computing with Spin Torque Devices
Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra
Abstract icon PDF icon Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic
Swarup Bhunia, Vaishnavi Ranganathan, Tina He, Srihari Rajgopal, Rui Yang, Mehran Mehregany, Philip X.-L. Feng

9.1 Hot Topic: CMOS Scaling - from Evolutionary to Revolutionary Computing

Organizers: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR
Chairs: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR

Abstract icon PDF icon III-V Semiconductor Nanowires for Future Devices
H. Schmid, B.M. Borg, K. Moselund, P. Das Kunungo, G. Signorello, S. Karg, P. Mensch, V. Schmidt, H. Riel
Abstract icon PDF icon Advanced System on a Chip Design Based on Controllable-Polarity FETs
Pierre-Emmanuel Gaillardon, Luca Amaru, Jian Zhang, Giovanni De Micheli
Abstract icon PDF icon Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges
Walter M. Weber, Jens Trommer, Matthias Grube, André Heinzig, Markus König, Thomas Mikolajick
Abstract icon PDF icon Advancing CMOS with Carbon Electronics
Franz Kreupl

9.2 Low-Cost, High-Performance NoCs

Chairs: Kees Goossens, Eindhoven University, NL; Luca Ramini, University of Ferrara, IT

Abstract icon PDF icon Application Mapping for Express Channel-Based Networks-on-Chip
Di Zhu, Lizhong Chen, Siyu Yue, Massoud Pedram
Abstract icon PDF icon Parallel Probe Based Dynamic Connection Setup in TDM NoCs
Shaoteng Liu, Axel Jantsch, Zhonghai Lu
Abstract icon PDF icon ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers
I. Seitanidis, A. Psarras, G. Dimitrakopoulos, C. Nicopoulos
Abstract icon PDF icon Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs
Marta Ortín, Darío Suárez, María Villarroya, Cruz Izu, Víctor Viñals
Abstract icon PDF icon Improving Hamiltonian-based Routing Methods for On-chip Networks: A Turn Model Approach
Poona Bahrebar, Dirk Stroobandt

9.3 Hardware Implementations for Data Security

Chairs: Viktor Fischer, St Etienne, FR; Filippo Melzani, STMicroelectronics, IT

Abstract icon PDF icon Embedded Reconfigurable Logic for ASIC Design Obfuscation against Supply Chain Attacks
Bao Liu, Brandon Wang
Abstract icon PDF icon A Minimalist Approach to Remote Attestation
Aurélien Francillon, Quan Nguyen, Kasper B. Rasmussen, Gene Tsudik
Abstract icon PDF icon Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support
Pranav Koundinya, Sandhya Theril, Tao Feng, Varun Prakash, Jiming Bao, Weidong Shi
Abstract icon PDF icon HEROIC: Homomorphically EncRypted One Instruction Computer
Nektarios Georgios Tsoutsos, Michail Maniatakos
Abstract icon PDF icon EDA Tools Trust Evaluation through Security Property Proofs
Yier Jin

9.4 Timing challenges in validation

Chairs: Elena Ioana Vatajelu, Politecnico di Torino, IT; Mark Zwolinski, University of Southampton, UK

Abstract icon PDF icon Fast STA Prediction-based Gate-level Timing Simulation
Tariq B. Ahmad, Maciej J. Ciesielski
Abstract icon PDF icon A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors
V. Guarnieri, M. Petricca, A. Sassone, S. Vinco, N. Bombieri, F. Fummi, E. Macii, M. Poncino
Abstract icon PDF icon Empowering Study of Delay Bound Tightness with Simulated Annealing
Xueqian Zhao, Zhonghai Lu
Abstract icon PDF icon Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models
Yanchen Long, Zhonghai Lu, Xiaolang Yan

9.5 Hot Topic: Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test

Organizers: Ulf Schlichtmann, Technische Universität München, DE; Andreas Herkersdorf, Technische Universität München, DE
Chairs: Nikil Dutt, University of California, Irvine, US; Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Abstract icon PDF icon Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test
Ulf Schlichtmann, Veit B. Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaβ, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn

9.6 Schedulability Analysis

Chair: Rob Davis, University of York, UK; Giuseppe Lipari, ENS - Cachan, FR

Abstract icon PDF icon Rate-Adaptive Tasks: Model, Analysis, and Design Issues
Giorgio C. Buttazzo, Enrico Bini, Darren Buttle
Abstract icon PDF icon Acceptance and Random Generation of Event Sequences under Real Time Calculus Constraints
Kajori Banerjee, Pallab Dasgupta
Abstract icon PDF icon General and Efficient Response Time Analysis for EDF Scheduling
Nan Guan, Wang Yi
Abstract icon PDF icon The Schedulability Region of Two-Level Mixed-Criticality Systems Based on EDF-VD
Dirk Müller, Alejandro Masrur

9.7 Timing Analysis and Cell Design

Chairs: Jose Monteiro, INESC-ID / Tecnico, ULisboa, PT; Elena Dubrova, Royal Institute of Technology, SE

Abstract icon PDF icon Facilitating Timing Debug by Logic Path Correspondence
Oshri Adler, Eli Arbel, Ilia Averbouch, Ilan Beer, Inna Grijnevitch
Abstract icon PDF icon Statistical Static Timing Analysis Using a Skew-Normal Canonical Delay Model
Vijaykumar M, V Vasudevan
Abstract icon PDF icon Leakage-Power-Aware Clock Period Minimization
Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh
Abstract icon PDF icon A Deep Learning Methodology to Proliferate Golden Signoff Timing
Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan
Abstract icon PDF icon Aging-aware Standard Cell Library Design
Saman Kiamehr, Farshad Firouzi, Mojtaba Ebrahimi, Mehdi B. Tahoori
Abstract icon PDF icon Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits
Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
Abstract icon PDF icon Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs
Kitae Park, Geunho Kim, Taewhan Kim

9.8 Embedded Tutorial: Memcomputing: The Cape of Good Hope

Organizers: Yiyu Shi, Missouri University of Science & Technology, US; Hung-Ming Chen, National Chiao Tung University,Taiwan
Chairs: Yiyu Shi, Missouri University of Science & Technology, US; Hung-Ming Chen, National Chiao Tung University,Taiwan, Taiwan

Abstract icon PDF icon Memcomputing: The Cape of Good Hope
Yiyu Shi, Hung-Ming Chen
Abstract icon PDF icon MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies
Chun Zhang, Peng Deng, Hui Geng, Jianming Liu, Qi Zhu, Jinjun Xiong, Yiyu Shi
Abstract icon PDF icon Energy-Efficient Hardware Acceleration through Computing in the Memory
Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri

10.1 Hot Topic: Memories Today and Tomorrow

Organizers: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR
Chairs: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE

Abstract icon PDF icon Exploring the Limits of Phase Change Memories
Matthias Wuttig
Abstract icon PDF icon Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips
G. Prenat, G. Di Pendina, C. Layer, O. Goncalves, K. Jaber, B. Dieny, R. Sousa, I.L. Prejbeanu, J.P. Nozieres
Abstract icon PDF icon Resistive Memories: Which Applications?
Fabien Clermidy, Natalija Jovanovic, Santhosh Onkaraiah, Houcine Oucheikh, Olivier Thomas, Ogun Turkyilmaz, Elisa Vianello, Jean-Michel Portal, Marc Bocquet
Abstract icon PDF icon Thinfilm Printed Ferro-Electric Memories and Integrated Products
Christer Karlsson, Peter Fischer

10.2 Wireless NoCs

Chairs: Giorgos Dimitrakopoulos, Democritus University of Thrace, GR; Valeria Bertacco, University of Michigan, US

Abstract icon PDF icon An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs
Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania
Abstract icon PDF icon Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies
Paul Wettin, Jacob Murray, Ryan Kim, Xinmin Yu, Partha Pratim Pande, Deukhyoun Heo
Abstract icon PDF icon Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips
Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano
Abstract icon PDF icon Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip
Ammar Karkar, Nizar Dahir, Ra'ed Al-Dujaily, Kenneth Tong, Terrence Mak, Alex Yakovlev
Abstract icon PDF icon Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems
Eberle A Rambo, Alexander Tschiene, Jonas Diemer, Leonie Ahrendts, Rolf Ernst

10.3 Green Computing Systems

Chairs: Ayse Coskun, Boston University, US; Martino Ruggiero, University of Bologna, IT

Abstract icon PDF icon Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers
Jungsoo Kim, Mohamed M. Sabry, David Atienza, Kalyan Vaidyanathan, Kenny Gross
Abstract icon PDF icon Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World
Andrea Bartolini, Matteo Cacciari, Carlo Cavazzoni, Giampietro Tecchiolli, Luca Benini
Abstract icon PDF icon Contention Aware Frequency Scaling on CMPs with Guaranteed Quality of Service
Hao Shen, Qinru Qiu
Abstract icon PDF icon Concurrent Placement, Capacity Provisioning, and Request Flow Control for a Distributed Cloud Infrastructure
Shuang Chen, Yanzhi Wang, Massoud Pedram
Abstract icon PDF icon COOLIP: Simple yet Effective Job Allocation for Distributed Thermally-Throttled Processors
Pratyush Kumar, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele
Abstract icon PDF icon Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh
Mohammadsadegh Sadri, Matthias Jung, Christian Weis, Norbert Wehn, Luca Benini

10.4 System-level Evaluation

Chairs: Pablo Sanchez, University of Cantabria, ES Florian Letombe, Synopsys, FR

Abstract icon PDF icon Automatic Detection of Concurrency Bugs through Event Ordering Constraints
Luis Gabriel Murillo, Simon Wawroschek, Jeronimo Castrillon, Rainer Leupers, Gerd Ascheid
Abstract icon PDF icon Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs
Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran
Abstract icon PDF icon SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives
Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Salvatore Galfano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Pirero Olivo, Davide Bertozzi
Abstract icon PDF icon Efficient Simulation and Modelling of Non-rectangular NoC Topologies
Ji Qi, Mark Zwolinski
Abstract icon PDF icon Moving from Co-Simulation to Simulation for Effective Smart Systems Design
Franco Fummi, Michele Lora, Francesco Stefanni, Dimitrios Trachanis, Jan Vanhese, Sara Vinco

10.5 Analysis of Components and Systems

Chairs: Frank Oppenheimer, OFFIS, DE; Todor Stefanov, Leiden University, NL

Abstract icon PDF icon May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models
Weiwei Chen, Xu Han, Rainer Dömer
Abstract icon PDF icon Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs
R.M.W.Frijns, S.Adyanthaya, S.Stuijk, J.P.M.Voeten, M.C.W.Geilen, R.R.H.Schiffelers, H.Corporaal
Abstract icon PDF icon A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures
Sébastien Le Nours, Adam Postula, Neil W. Bergmann
Abstract icon PDF icon Cross-correlation of Specification and RTL for Soft IP Analysis
Bhanu Singh, Arunprasath Shankar, Francis Wolff, Christos Papachristou, Daniel Weyer, Steve Clay

10.6 Multi-processor and Distributed Systems

Chairs: Orlando Moreira, Ericsson, NL; Benny Akesson, CTU, CZ

Abstract icon PDF icon Thermal-Aware Frequency Scaling for Adaptive Workloads on Heterogeneous MPSoCs
Heng Yu, Rizwan Syed, Yajun Ha
Abstract icon PDF icon Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms
Chuancai Gu, Nan Guan, Qingxu Deng, Wang Yi
Abstract icon PDF icon Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications
Akramul Azim, Gonzalo Carvajal, Rodolfo Pellizzoni, Sebastian Fischmeister

10.7 Advances in Synthesis

Chairs: John Hayes, University of Michigan, US; Kim Taemin, Intel Labs, US

Abstract icon PDF icon Provably Minimal Energy Using Coordinated DVS and Power Gating
Nathaniel A. Conos, Saro Meguerdichian, Foad Dabiri, Miodrag Potkonjak
Abstract icon PDF icon A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments
Syed Rameez Naqvi, Andreas Steininger
Abstract icon PDF icon An Efficient Manipulation Package for Biconditional Binary Decision Diagrams
Luca Amarú, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Abstract icon PDF icon Synthesis Algorithm of Parallel Index Generation Units
Yusuke Matsunaga
Abstract icon PDF icon Automating Data Reuse in High-Level Synthesis
Wim Meeus, Dirk Stroobandt
Abstract icon PDF icon A Universal Symmetry Detection Algorithm
Peter M. Maurer
Abstract icon PDF icon Optimization of Design Complexity in Time-Multiplexed Constant Multiplications
Levent Aksoy, Paulo Flores, José Monteiro
Abstract icon PDF icon Hardware Primitives for the Synthesis of Multithreaded Elastic Systems
G. Dimitrakopoulos, I. Seitanidis, A. Psarras, K. Tsiouris, P. Mattheakis, J. Cortadella

11.0 Special Day Keynote: Organic Electronics - From Lab to Markets

Abstract icon PDF icon Karl Leo - Technische Universität Dresden, DE

 

11.1 Embedded Tutorial: Alternatives to CMOS

Organizers: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE
Chairs: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE

Abstract icon PDF icon Spintronics for Low-Power Computing
Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafiné Ravelosona, Claude Chappert
Abstract icon PDF icon CHAMELEON: CHANNEL Efficient Optical Network-on-Chip
Sébastien Le Beux, Hui Li, Ian O'Connor, Kazem Cheshmi, Xuchen Liu, Jelena Trajkovic, Gabriela Nicolescu
Abstract icon PDF icon Low-Voltage Organic Transistors for Flexible Electronics
Ute Zschieschang, Reinhold Rödel, Ulrike Kraft, Kazuo Takimiya, Tarek Zaki, Florian Letzkus, Jörg Butschke, Harald Richter, Joachim N. Burghartz, Wei Xiong, Boris Murmann, Hagen Klauk

11.2 Transitioning NoC Design Techniques to Future Challenges

Chairs: Masoud Daneshtalab, University of Turku, FI; Hiroki Matsutani, Keio University, JP

Abstract icon PDF icon Brisk and Limited-Impact NoC Routing Reconfiguration
Doowon Lee, Ritesh Parikh, Valeria Bertacco
Abstract icon PDF icon Thermal Management of Manycore Systems with Silicon-Photonic Networks
Tiansheng Zhang, José L. Abellán, Ajay Joshi, Ayse K. Coskun
Abstract icon PDF icon Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline
Luca Ramini, Paolo Grani, Hervé Tatenguem Fankem, Alberto Ghiribaldi, Sandro Bartolini, Davide Bertozzi
Abstract icon PDF icon DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs.
Wolfgang Büter, Christof Osewold, Daniel Gregorek, Alberto García-Ortiz
Abstract icon PDF icon Minimally Buffered Single-Cycle Deflection Router
Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam

11.3 Industry Relevant Research and Practice for System Design

Chairs: Emil Matus, Technische Universität Dresden, DE; Norbert Wehn, TU Kaiserslautern. DE

Abstract icon PDF icon The Metamodeling Approach to System Level Synthesis
Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal
Abstract icon PDF icon Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling
Yu Pu, Juan Echeverri, Maurice Meijer, Jose Pineda de Gyvez
Abstract icon PDF icon Formal Verification of Taint-propagation Security Properties in a Commercial SoC Design
Pramod Subramanyan, Divya Arora
Abstract icon PDF icon Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case
Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Alexandre Aminot, Pascal Vivet, Hela Boussetta, Luca Ferro, Nicolas Peltier
Abstract icon PDF icon Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems
Arquimedes Canedo, Mohammad Abdullah Al Faruque, Jan H. Richter
Abstract icon PDF icon Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy
Seiyang Yang, Jaehoon Han, Doowhan Kwak, Namdo Kim, Daeseo Cha, Junhyuck Park, Jay Kim

11.4 Enabling validation on fast platforms

Chairs: Ronny Morad, IBM, IL; Franco Fummi, Universita' di Verona, IT

Abstract icon PDF icon ArChiVED: Architectural Checking via Event Digests for High Performance Validation
Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco
Abstract icon PDF icon Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes
Kai Cong, Li Lei, Zhenkun Yang, Fei Xie
Abstract icon PDF icon Effective Post-Silicon Failure Localization Using Dynamic Program Slicing
Ophir Friedler, Wisam Kadry, Arkadiy Morgenshtein, Amir Nahir, Vitali Sokhin
Abstract icon PDF icon Design-for-Debug Routing for FIB Probing
Chia-Yi Lee, Tai-Hung Li, Tai-Chen Chen
Abstract icon PDF icon Functional Test Generation Guided by Steady-State Probabilities of Abstract Design
Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li
Abstract icon PDF icon Automated System Testing Using Dynamic and Resource Restricted Clients
Mirko Caspar, Mirko Lippmann, Wolfram Hardt

11.5 Memory Resource Allocation and Scheduling in MPSoC

Chairs: Andreas Herkersdorf, Technische Universität Munchen, DE; Donatella Sciuto, Politecnico di Milano,IT

Abstract icon PDF icon Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs
Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang
Abstract icon PDF icon Optimized Buffer Allocation in Multicore Platforms
Maximilian Odendahl, Andrés Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson
Abstract icon PDF icon Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming
Xue-Yang Zhu, Marc Geilen, Twan Basten, Sander Stuijk
Abstract icon PDF icon A Constraint-Based Design Space Exploration Framework for Real-Time Applications on MPSoCs
Kathrin Rosvall, Ingo Sander
Abstract icon PDF icon Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality
Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele
Abstract icon PDF icon From Simulink to NoC-based MPSoC on FPGA
Francesco Robino, Johnny Öberg

11.6 System-Level Thermal Estimation and Management

Chairs: Coskun Ayse, Boston University, US; Wolfgang Nebel, OFFIS, DE

Abstract icon PDF icon Minimal Sparse Observability of Complex Networks: Application to MPSoC Sensor Placement and Run-time Thermal Estimation & Tracking
Santanu Sarma, Nikil Dutt
Abstract icon PDF icon mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems
Heba Khdr, Thomas Ebi, Muhammad Shafique, Hussam Amrouch, Jörg Henkel
Abstract icon PDF icon Thermal Management of Batteries Using a Hybrid Supercapacitor Architecture
Donghwa Shin, Massimo Poncino, Enrico Macii
Abstract icon PDF icon Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip
Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Denis Dutoit, Luca Benini
Abstract icon PDF icon Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model
Xiaohang Wang, Baoxin Zhao, Terrence Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Maurizio Palesi
Abstract icon PDF icon Unified, Ultra Compact, Quadratic Power Proxies for Multi-Core Processors
Muhammad Yasin, Anas Shahrour, Ibrahim (Abe) M. Elfadel

11.7 Power and Emerging Technologies in Reconfigurable Computing

Chairs: Diana Goehringer, Ruhr-University Bochum (RUB), DE; Fabrizio Ferrandi, Politecnico di Milano, IT

Abstract icon PDF icon Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design
Adarsh Reddy Ashammagari, Hamid Mahmoodi, Houman Homayoun
Abstract icon PDF icon A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology
Ali Ahari, Hossein Asadi, Behnam Khaleghi, Mehdi B. Tahoori
Abstract icon PDF icon Extending Lifetime of Battery-Powered Coarse-Grained Reconfigurable Computing Platforms
Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei
Abstract icon PDF icon 3D FPGA Using High-density Interconnect Monolithic Integration
Ogun Turkyilmaz, Gérald Cibrario, Olivier Rozeau, Perrine Batude, Fabien Clermidy
Abstract icon PDF icon Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
Abstract icon PDF icon A Novel Embedded System for Vision Tracking
Antonis Nikitakis, Theofilos Paganos, Ioannis Papaefstathiou

11.8 Embedded Tutorial: GPGPUs: How to Combine High Computational Power with High Reliability

Organizesr: Matteo Sonza Reorda, Politecnico di Torino, IT
Chairs: Dimitris Gizopoulos, University of Athens, GR; Rob Aitken, ARM, US

Abstract icon PDF icon GPGPUs: How to Combine High Computational Power with High Reliability
L. Bautista Gomez, F. Cappello, L. Carro, N. DeBardeleben, B. Fang, S. Gurumurthi, K. Pattabiraman, P. Rech, M. Sonza Reorda

12.1 Hot Topic: The Future of Interfacing to the Natural World

Organizers: Ian O'Connor, Lyon Institute of Nanotechnology, FR; Thomas Mikolajick, NamLab gGmbH, DE
Chairs: Thomas Mikolajick, NamLab gGmbH, DE; Ian O'Connor, Lyon Institute of Nanotechnology, FR

Abstract icon PDF icon Integrated Circuits Processing Chemical Information: Prospects and Challenges
A. Richter, A. Voigt, R. Schüffny, S. Henker, M. Völp
Abstract icon PDF icon Interfacing to Living Cells
Rudy Lauwereins
Abstract icon PDF icon Video Analytics Using Beyond CMOS Devices
Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Don Chiarulli, Steve Levitan, Philip Wong
Abstract icon PDF icon Energy Efficient Neural Networks for Big Data Analytics
Yu Wang, Boxun Li, Rong Luo, Yiran Chen, Ningyi Xu, Huazhong Yang

12.2 Hot topic: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks

Organizer: Ulrich Rührmair, TU München, DE
Chair: Ulf Schlichtmann, TU München, DE

Abstract icon PDF icon Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks
Ulrich Rührmair, Ulf Schlichtmann, Wayne Burleson
Abstract icon PDF icon PUFs at a Glance
Ulrich Rührmair, Daniel E. Holcomb
Abstract icon PDF icon PUF Modeling Attacks: An Introduction and Overview
Ulrich Rührmair, Jan Sölter
Abstract icon PDF icon Hybrid Side-Channel / Machine-Learning Attacks on PUFs: A New Threat?
Xiaolin Xu, Wayne Burleson
Abstract icon PDF icon Physical Vulnerabilities of Physically Unclonable Functions
Clemens Helfmeier, Christian Boit, Dmitry Nedospasov, Shahin Tajik, Jean-Pierre Seifert
Abstract icon PDF icon Protocol Attacks on Advanced PUF Protocols and Countermeasures
Marten van Dijk, Ulrich Rührmair
Abstract icon PDF icon Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder Based Security
Masoud Rostami, James B. Wendt, Miodrag Potkonjak, Farinaz Koushanfar

12.3 Multimedia Systems

Chairs: Theocharides Theocharis, University of Cyprus, CY; Cristiana Bolchini, Politecnico di Milano, IT

Abstract icon PDF icon Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs
Hong Chinh Doan, Haris Javaid, Sri Parameswaran
Abstract icon PDF icon A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications
Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue
Abstract icon PDF icon Image Progressive Acquisition for Hardware Systems
Jianxiong Liu, Christos Bouganis, Peter Y.K. Cheung
Abstract icon PDF icon High-Quality Real-Time Hardware Stereo Matching Based on Guided Image Filtering
Christos Ttofis, Theocharis Theocharides

12.4 Physical Aspects

Chair: Carl Sechen, University of Texas at Dallas, US; Jens Lienig, TU Dresden, DE

Abstract icon PDF icon Optimization of Standard Cell Based Detailed Placement for 16 nm FinFET Process
Yuelin Du, Martin D. F. Wong
Abstract icon PDF icon Signature Indexing of Design Layouts for Hotspot Detection
Cristian Andrades, M. Andrea Rodríguez, Charles C. Chiang
Abstract icon PDF icon Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost
Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang

12.5 System-level Design Space Exploration

Chairs: Frederic Petrot, TIMA, FR; Luciano Lavagno, Politecnico di Torino, IT

Abstract icon PDF icon Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures
Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaβ, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich
Abstract icon PDF icon ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits
Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda
Abstract icon PDF icon Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism
Taemin Kim, Yatin Hoskote
Abstract icon PDF icon System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach
Emanuele Cannella, Mohamed A. Bamakhrama, Todor Stefanov

12.6 Error Resilience and Power Management

Chairs: William Fornaciari, Politecnico di Milano - DEIB, IT; Kim Gruettner, OFFIS, DE

Abstract icon PDF icon ASLAN: Synthesis of Approximate Sequential Circuits
Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
Abstract icon PDF icon VRCon: Dynamic Reconfiguration of Voltage Regulators in a Multicore Platform
Woojoo Lee, Yanzhi Wang, Massoud Pedram
Abstract icon PDF icon Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs
Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee
Abstract icon PDF icon FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring
Kitae Kim, Donghwa Shin, Qing Xie, Yanzhi Wang, Massoud Pedram, Naehyuck Chang

12.7 Built-in Self-test Solutions for Mixed-signal and RF ICs

Chairs: Jacob A. Abraham, University of Texas at Austin, US; Marian Verhelst, KU Leuven, BE

Abstract icon PDF icon An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions
Dzmitry Maliuk, Yiorgos Makris
Abstract icon PDF icon Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode
Jae Woong Jeong, Sule Ozev, Shreyas Sen, Vishwanath Natarajan, Mustapha Slamani
Abstract icon PDF icon A Flexible BIST Strategy for SDR Transmitters
Emanuel Dogaru, Filipe Vinci dos Santos, William Rebernak
Abstract icon PDF icon Sigma-Delta Testability for Pipeline A/D Converters
Antonio Gines, Gildas Leger

12.8 Panel: Future SoC Verification Methodology: UVM Evolution or Revolution?

Organizer: Alex Goryachev, IBM Research - Haifa, IL
Chair: Rolf Drechsler, University of Bremen/DFKI,DE

Abstract icon PDF icon Future SoC Verification Methodology: UVM Evolution or Revolution?
Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev