[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Abelein, Ulrich

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1

Abella, Jaume

Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2

Abellán, José L.

Thermal Management of Manycore Systems with Silicon-Photonic Networks 11.2_2

Abraham, Jacob A.

A Novel Low Power 11-bit Hybrid ADC Using Flash and Delay Line Architectures - 02.4_6

Abraham, Jacob A.

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Acquaviva, Jean-Thomas

A Unified Methodology for a Fast Benchmarking of Parallel Architecture - 07.6_7

Adam, Daniel

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Adler, Oshri

Facilitating Timing Debug by Logic Path Correspondence - 09.7_1

Adyanthaya, S.

Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2

Afacan, Engin

Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5

Afzali Kusha, Ali

Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits - 05.4_5

Afzali-Kusha, Ali

Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions - 08.6_7

Agbo, Innocent

Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2

Aghaee, Nima

An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs - 05.7_5

Agrawal, Prashant

Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5

Agrawal, Supriya

EDT: A Specification Notation for Reactive Systems - 08.5_3

Aguilera, Paula

Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4

Ahari, Ali

A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology - 11.7_2

Ahmad, Tariq B.

Fast STA Prediction-based Gate-level Timing Simulation - 09.4_1

Ahmad, Ubaid

Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1

Ahrendts, Leonie

Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5

Aitken, Rob

Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2

Akesson, Benny

Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems - 03.5_1

Akesson, Benny

Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1

Aksanli, Baris

Providing Regulation Services and Managing Data Center Peak Power Budgets - 06.3_6

Aksoy, Levent

Optimization of Design Complexity in Time-Multiplexed Constant Multiplications - 10.7_7

Al Faruque, Mohammad Abdullah

GPU-EvR: Run-time Event Based Real-time Scheduling Framework on GPGPU Platform - 08.6_2

Al Faruque, Mohammad Abdullah

Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems - 11.3_5

Alaghi, Armin

Fast and Accurate Computation Using Stochastic Circuits - 04.4_4

Alam, Faisal

Energy Optimization in Android Applications through Wakelock Placement - 04.6_5

Al-Dujaily, Ra'ed

Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4

Alekseyev, Arseniy

Design of Safety Critical Systems by Refinement - 04.6_4

Alexandrescu, Dan

Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1

Alexandrescu, Dan

INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4

Alhammad, Ahmed

Time-predictable Execution of Multithreaded Applications on Multicore Systems - 02.6_4

Al-Hashimi, Bashir M.

Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6

Al-Hashimi, Bashir M.

Clock-Modulation Based Watermark for Protection of Embedded Processors - 03.3_3

Alì, Giuseppe

Implicit Index-aware Model Order Reduction for RLC/RC Networks 03.4_3

Alizadeh, Bijan

Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits - 05.4_5

Alorda, B.

Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications - 06.7_2

Althaus, Ernst

Simple Interpolants for Linear Arithmetic - 05.5_3

Altmeyer, Sebastian

On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis - 02.6_1

Amano, Hideharu

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Amano, Hideharu

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Amaru, Luca

Advanced System on a Chip Design Based on Controllable-Polarity FETs - 09.1_2

Amarú, Luca

An Efficient Manipulation Package for Biconditional Binary Decision Diagrams - 10.7_3

Aminifar, Amir

Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees - 03.6_2

Aminot, Alexandre

Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4

Amir, Mohammad Faisal

Ultra-low Power Electronics with Si/Ge Tunnel FET - 08.8_1

Amrouch, Hussam

hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6

Amrouch, Hussam

mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2

Andrades, Cristian

Signature Indexing of Design Layouts for Hotspot Detection - 12.4_2

Annaswamy, Anuradha M.

Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3

Annavaram, Murali

Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W - 05.3_2

Ansaloni, Giovanni

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1

Anton, Mario

Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2

Antoniadis, Dimitri

Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1

Araújo, Guido

Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5

Arbel, Eli

Facilitating Timing Debug by Logic Path Correspondence - 09.7_1

Arora, Divya

Formal Verification of Taint-propagation Security Properties in a Commercial SoC Design - 11.3_3

Asadi, Hossein

A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology - 11.7_2

Ashammagari, Adarsh Reddy

Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design - 11.7_1

Ascheid, Gerd

Time-Decoupled Parallel SystemC Simulation - 07.6_6

Ascheid, Gerd

Automatic Detection of Concurrency Bugs through Event Ordering Constraints - 10.4_1

Ascheid, Gerd

Optimized Buffer Allocation in Multicore Platforms - 11.5_2

Ascheid, Gerd

A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2

Ascia, Giuseppe

An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs - 10.2_1

Atienza, David

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2

Atienza, David

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1

Atienza, David

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4

Atienza, David

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3

Atienza, David

Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1

Averbouch, Ilia

Facilitating Timing Debug by Logic Path Correspondence - 09.7_1

Ay, Simge

Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5

Ayari, H.

New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7

Aysu, Aydin

Analyzing and Eliminating the Causes of Fault Sensitivity Analysis - 08.3_2

Azais, F.

New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7

Azevedo, Rodolfo

Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5

Azim, Akramul

Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications - 10.6_3

B

Bacivarov, Iuliana

COOLIP: Simple yet Effective Job Allocation for Distributed Thermally-Throttled Processors - 10.3_5

Bacivarov, Iuliana

Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5

Baghdadi, Amer

Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL - 08.4_2

Bahar, R. Iris

ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits - 12.5_2

Bähr, Steffen

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Bahrebar, Poona

Improving Hamiltonian-based Routing Methods for On-chip Networks: A Turn Model Approach - 09.2_5

Bai, Yu

Isochronous Networks by Construction - 06.6_2

Balachandran, Shankar

Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control - 04.5_3

Balck, Kenneth

Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP - 07.6_5

Bamakhrama, Mohamed A.

System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach - 12.5_4

Bampi, Sergio

dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2

Banagaaya, Nicodemus

Implicit Index-aware Model Order Reduction for RLC/RC Networks 03.4_3

Bandinu, M.

Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications - 03.4_1

Banerjee, Kajori

Acceptance and Random Generation of Event Sequences under Real Time Calculus Constraints - 09.6_2

Bao, Jiming

Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3

Bapp, Falco

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Bardizbanyan, Alen

Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD³) - 04.5_6

Barke, E.

Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4

Bartolini, Andrea

A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5

Bartolini, Andrea

Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2

Bartolini, Andrea

Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2

Bartolini, Andrea

Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4

Bartolini, Sandro

Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3

Baskaya, Faik

Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5

Basten, Twan

Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming - 11.5_3

Batude, Perrine

3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4

Bautista Gomez, L.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Bazargan, Kia

IIR Filters Using Stochastic Arithmetic - 04.4_1

Becker, Andrew

SKETCHILOG: Sketching Combinational Circuits - 06.5_5

Becker, Bernd

Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1

Becker, Bernd

An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3

Becker, Bernd

Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1

Becker, Jürgen

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Beer, Ilan

Facilitating Timing Debug by Logic Path Correspondence - 09.7_1

Beerel, Peter

Stochastic Analysis of Bubble Razor - 05.4_3

Beltrame, Giovanni

Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias - 04.4_2

Beneventi, Francesco

Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4

Benini, Luca

A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7

Benini, Luca

A Multi Banked - Multi Ported - non Blocking Shared L2 Cache for MPSoC Platforms 04.5_4

Benini, Luca

Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs - 05.3_1

Benini, Luca

A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5

Benini, Luca

Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3

Benini, Luca

Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2

Benini, Luca

Context Aware Power Management for Motion-sensing Body Area Network Nodes - 07.3_3

Benini, Luca

Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2

Benini, Luca

Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh - 10.3_6

Benini, Luca

Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4

Beretta, Ivan

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1

Bergmann, Neil W.

A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures 10.5_3

Bernard, Florent

On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models - 03.3_2

Bernard, S.

New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7

Bernardi, Paolo

An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3

Beroulle, Vincent

A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4

Bertacco, Valeria

Brisk and Limited-Impact NoC Routing Reconfiguration - 11.2_1

Bertacco, Valeria

ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1

Bertozzi, Davide

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3

Bertozzi, Davide

Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3

Beyranvand Nejad, Ashkan

CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4

Bhargava, Mudit

An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS - 04.3_2

Bhunia, Swarup

Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3

Bhunia, Swarup

Energy-Efficient Hardware Acceleration through Computing in the Memory - 09.8_3

Biewer, Alexander

A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving - 08.5_5

Bin Nasir, Saad

Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3

Bini, Enrico

Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees - 03.6_2

Bini, Enrico

Rate-Adaptive Tasks: Model, Analysis, and Design Issues - 09.6_1

Bishnoi, Rajendra

Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM - 07.5_1

Bocquet, Marc

Resistive Memories: Which Applications? - 10.1_4

Boettcher, Matthias

Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6

Bogdan, Paul

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Boit, Christian

Physical Vulnerabilities of Physically Unclonable Functions - 12.2_5

Bolchini, C.

Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs - 03.7_2

Bolle, Michael

The Connected Car and Its Implication to the Automotive Chip Roadmap - 07.0

Bombieri, N.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2

Boning, Duane

Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1

Borg, B.M.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Bortolotti, Daniele

Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2

Bota, S.

Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications - 06.7_2

Bouganis, Christos

Image Progressive Acquisition for Hardware Systems - 12.3_3

Bournoutian, Garo

On-Device Objective-C Application Optimization Framework for High-Performance Mobile Processors - 04.6_2

Boussetta, Hela

Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4

Braojos, Rubén

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1

Bringmann, Oliver

Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3

Brück, Rainer

System Integration - The Bridge between More than Moore and More Moore - 05.8

Brunelli, Davide

Real-time Optimization of the Battery Banks Lifetime in Hybrid Residential Electrical Systems - 06.3_2

Burg, Andreas

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4

Burger, Andreas

Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3

Burger, Doug

EVX: Vector Execution on Low Power EDGE Cores - 02.5_4

Burghartz, Joachim N.

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Burgio, Paolo

A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7

Burgio, Paolo

Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3

Burleson, Wayne

Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks - 12.2_1

Burleson, Wayne

Hybrid Side-Channel / Machine-Learning Attacks on PUFs: A New Threat? - 12.2_4

Burlyaev, Dmitry

Verification-guided Voter Minimization in Triple-Modular Redundant Circuits - 04.7_2

Büter, Wolfgang

DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs. - 11.2_4

Butschke, Jörg

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Buttazzo, Giorgio C.

Rate-Adaptive Tasks: Model, Analysis, and Design Issues - 09.6_1

Buttle, Darren

Rate-Adaptive Tasks: Model, Analysis, and Design Issues - 09.6_1

C

Cabodi, G.

Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization - 05.5_4

Cacciari, Matteo

Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2

Calimera, Andrea

Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits - 09.7_7

Canal, Ramon

SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis - 02.7_3

Canal, Ramon

INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4

Canal, Ramon

DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy - 04.5_5

Canedo, Arquimedes

Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems - 11.3_5

Canelas, António

Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1

Cannella, Emanuele

System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach - 12.5_4

Caplan, Jonah

Trade-offs in Execution Signature Compression for Reliable Processor Systems - 04.7_3

Cappello, F.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Carmona, C.

Word-Line Power Supply Selector for Stability Improvement of Embedded SRAMs in High Reliability Applications - 06.7_2

Carro, L.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Carvajal, Gonzalo

Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications - 10.6_3

Casamassima, Filippo

Context Aware Power Management for Motion-sensing Body Area Network Nodes - 07.3_3

Caspar, Mirko

Automated System Testing Using Dynamic and Resource Restricted Clients - 11.4_6

Castellana, Vito Giovanni

An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems - 07.4_7

Castrillon, Jeronimo

Automatic Detection of Concurrency Bugs through Event Ordering Constraints - 10.4_1

Castro-López, R.

Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits - 02.4_3

Catania, Vincenzo

An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs - 10.2_1

Catthoor, Francky

Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3

Catthoor, Francky

Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2

Catthoor, Francky

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3

Catthoor, Francky

Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1

Catthoor, Francky

Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5

Cauwenberghs, Gert

Video Analytics Using Beyond CMOS Devices - 12.1_3

Cavazzoni, Carlo

Unveiling Eurora - Thermal and Power Characterization of the Most Energy-Efficient Supercomputer in the World - 10.3_2

Cazorla, Francisco J.

Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2

Cech, Christian

Power Modeling and Analysis in Early Design Phases - 08.1_1

Cha, Daeseo

Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6

Chakrabarty, Krishnendu

Multi-Site Test Optimization for Multi-V_dd SoCs Using Space- and Time-Division Multiplexing - 05.7_4

Chakraborty, Koushik

DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors - 03.7_3

Chakraborty, Samarjit

Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3

Chakraborty, Samarjit

Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3

Chandra, Vikas

Cross Layer Resiliency in Real World - 07.2

Chandramoorthy, Nandhini

Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2

Chandrasekar, Karthik

Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1

Chang, Doohwang

Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation - 02.7_6

Chang, Naehyuck

Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles - 05.4_4

Chang, Naehyuck

Optimal Design and Management of a Smart Residential PV and Energy Storage System - 06.3_4

Chang, Naehyuck

FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4

Chang, Ru-Hua

Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs - 11.5_1

Chang, Shih-Chieh

Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5

Chang, Shih-Chieh

Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6

Chang, Yuan-Hao

Garbage Collection for Multi-version Index on Flash Memory - 03.6_4

Chappert, Claude

Spintronics for Low-Power Computing - 11.1_1

Chatterjee, Debapriya

ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1

Chen, Chien-Hao

An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations - 08.5_1

Chen, Deming

Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3

Chen, Gang

Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3

Chen, Hu

DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors - 03.7_3

Chen, Hung-Ming

Cost-Effective Decap Selection for Beyond Die Power Integrity - 03.4_6

Chen, Hung-Ming

Memcomputing: The Cape of Good Hope - 09.8_1

Chen, Jian-Yu

Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints - 05.6_6

Chen, Kevin J.

Characterizing Power Delivery Systems with On/Off-Chip Voltage Regulators for Many-Core Processors - 03.4_7

Chen, Licheng

Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests - 04.5_1

Chen, Lizhong

Application Mapping for Express Channel-Based Networks-on-Chip - 09.2_1

Chen, Mingyu

Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests - 04.5_1

Chen, Qiuwen

Battery Aware Stochastic QoS Boosting in Mobile Computing Devices - 07.3_5

Chen, Shi-Hao

Cost-Effective Decap Selection for Beyond Die Power Integrity - 03.4_6

Chen, Shuang

Concurrent Placement, Capacity Provisioning, and Request Flow Control for a Distributed Cloud Infrastructure - 10.3_4

Chen, Shu-Yung

An Activity-Sensitive Contention Delay Model for Highly Efficient Deterministic Full-System Simulations - 08.5_1

Chen, Tai-Chen

Design-for-Debug Routing for FIB Probing - 11.4_4

Chen, Weiwei

May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models - 10.5_1

Chen, Yi-En

Cost-Effective Decap Selection for Beyond Die Power Integrity - 03.4_6

Chen, Yi-Hang

Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints - 05.6_6

Chen, Yi-Jung

Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs - 11.5_1

Chen, Ying-Yu

Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3

Chen, Yiran

ICE: Inline Calibration for Memristor Crossbar-based Computing Engine - 07.5_5

Chen, Yiran

Energy Efficient Neural Networks for Big Data Analytics - 12.1_4

Chen, Yi-Ting

Scenario-aware Data Placement and Memory Area Allocation for Multi-Processor System-on-Chips with Reconfigurable 3D-stacked SRAMs - 11.5_1

Chen, Yong

A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6

Chen, Yuankai

Recovery-Based Resilient Latency-Insensitive Systems - 05.3_4

Chen, Yu-Guang

Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6

Chen, Yung-Chih

Rewiring for Threshold Logic Circuit Minimization - 05.6_4

Chen, Yung-Chih

Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5

Cheng, Kwang-Ting

Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction - 08.7_2

Cheshmi, Kazem

CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2

Cheung, Peter Y.K.

Image Progressive Acquisition for Hardware Systems - 12.3_3

Chevallaz, Christophe

Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8

Chiang, Chang-En

Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5

Chiang, Charles C.

Signature Indexing of Design Layouts for Hotspot Detection - 12.4_2

Chiarulli, Don

Video Analytics Using Beyond CMOS Devices - 12.1_3

Chien, Hsi-An

Mask-Cost-Aware ECO Routing - 03.4_8

Chien, Jui-Hung

Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5

Chien, Tzu-Kai

Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost - 12.4_3

Childers, Bruce R.

Program Affinity Performance Models for Performance and Utilization - 02.5_5

Chinea, A.

Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications - 03.4_1

Cho, Yeongon

Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1

Cibrario, Gérald

3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4

Ciesielski, Maciej J.

Fast STA Prediction-based Gate-level Timing Simulation - 09.4_1

Ciganda, Lyl

An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3

Cilardo, Alessandro

Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems - 11.7_5

Clay, Steve

Cross-correlation of Specification and RTL for Soft IP Analysis - 10.5_4

Clediere, Jessy

Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1

Clermidy, Fabien

Resistive Memories: Which Applications? - 10.1_4

Clermidy, Fabien

3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4

Comte, M.

New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7

Cong, Kai

Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes - 11.4_2

Conos, Nathaniel A.

Provably Minimal Energy Using Coordinated DVS and Power Gating - 10.7_1

Conti, Francesco

Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3

Cook, Alejandro

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1

Corporaal, H.

Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2

Cortadella, J.

Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8

Cortez, Mafalda

Testing PUF-Based Secure Key Storage Circuits - 07.7_2

Coskun, Ayse K.

Thermal Management of Manycore Systems with Silicon-Photonic Networks 11.2_2

Costenaro, Enrico

Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1

Costenaro, Enrico

INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4

Coussy, Philippe

A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7

Cristal, Adrian

EVX: Vector Execution on Low Power EDGE Cores - 02.5_4

Crouch, Al

Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network - 07.7_3

D

Dabiri, Foad

Provably Minimal Energy Using Coordinated DVS and Power Gating - 10.7_1

Dahir, Nizar

Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4

Damodaran, Preethi P.

Distributed Cooperative Shared Last-Level Caching in Tiled Multiprocessor System on Chip - 04.5_7

Daneshtalab, Masoud

Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model - 11.6_5

Danger, Jean-Luc

Hacking and Protecting IC Hardware - 05.2

Danilo, Robin

A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7

Das, A.

Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs - 03.7_2

Das, Anup

Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia MPSoCs - 05.3_3

Dasgupta, Pallab

Acceptance and Random Generation of Event Sequences under Real Time Calculus Constraints - 09.6_2

Das Kunungo, P.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Datta, Suman

Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5

Datta, Suman

Video Analytics Using Beyond CMOS Devices - 12.1_3

Davis, Robert I.

On the Correctness, Optimality and Precision of Static Probabilistic Timing Analysis - 02.6_1

De Micheli, Giovanni

Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2

De Micheli, Giovanni

Advanced System on a Chip Design Based on Controllable-Polarity FETs - 09.1_2

De Micheli, Giovanni

An Efficient Manipulation Package for Biconditional Binary Decision Diagrams - 10.7_3

Deb, Abhijit

Startup Error Detection and Containment to Improve the Robustness of Hybrid FlexRay Networks - 02.3_2

DeBardeleben, N.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Dehbaoui, Amine

Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1

Del Bel, Brandon

Improving STT-MRAM Density through Multibit Error Correction - 07.5_3

Delvaux, Jeroen

Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation - 04.3_4

Deng, Peng

MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2

Deng, Qingxu

Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms - 10.6_2

Devitt, Simon

Software-based Pauli Tracking in Fault-tolerant Quantum Circuits - 05.6_7

Dhruva, Neil

Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems - 07.6_2

Di Carlo, Stefano

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3

Di Natale, Giorgio

Hacking and Protecting IC Hardware - 05.2

Di Natale, Giorgio

Testing PUF-Based Secure Key Storage Circuits - 07.7_2

Di Pendina, G.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Diemer, Jonas

Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5

Dieny, B.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Dietrich, Manfred

System Integration - The Bridge between More than Moore and More Moore - 05.8

Dimitrakopoulos, G.

ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers - 09.2_3

Dimitrakopoulos, G.

Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8

Ding, Huping

WCET-Centric Dynamic Instruction Cache Locking - 02.6_2

Dinh, Trung Anh

A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips - 04.4_3

Disch, Stefan

Simple Interpolants for Linear Arithmetic - 05.5_3

Doan, Hong Chinh

Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs - 12.3_1

Doboli, Alex

Novel Circuit Topology Synthesis Method Using Circuit Feature Mining and Symbolic Comparison - 02.4_8

Dogan, Ahmed

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes - 07.3_1

Dogaru, Emanuel

A Flexible BIST Strategy for SDR Transmitters - 12.7_3

Dömer, Rainer

May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models - 10.5_1

Domic, Antun

Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2

Dong, Chuansheng

Minimizing Stack Memory for Hard Real-time Applications on Multicore Platforms - 02.6_3

Dou, Wenhua

SAFE: Security-Aware FlexRay Scheduling Engine - 02.3_5

Drechsler, Rolf

Towards Verifying Determinism of SystemC Designs - 06.5_6

Drechsler, Rolf

Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8

Du, Yuelin

Optimization of Standard Cell Based Detailed Placement for 16 nm FinFET Process - 12.4_1

Duan, Guangshan

Exploiting Narrow-Width Values for Improving Non-Volatile Cache Lifetime - 03.5_4

Dubois, Michel

Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W - 05.3_2

Dündar, Günhan

Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5

Dupont de Dinechin, Benoît

Time-Critical Computing on a Single Chip Massively Parallel Processor - 05.1_2

Duric, Milovan

EVX: Vector Execution on Low Power EDGE Cores - 02.5_4

Dutertre, Jean-Max

Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1

Dutoit, Denis

Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip - 11.6_4

Dutt, Nikil

Minimal Sparse Observability of Complex Networks: Application to MPSoC Sensor Placement and Run-time Thermal Estimation & Tracking - 11.6_1

Duy, Viet Vu

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Dweik, Waleed

Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures W - 05.3_2

Dworak, Jennifer

Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network - 07.7_3

Dwyer, Chris

RETLab: A Fast Design-automation Framework for Arbitrary RET Networks - 05.6_1

E

Ebi, Thomas

mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2

Ebrahimi, Mojtaba

Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1

Ebrahimi, Mojtaba

Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM - 07.5_1

Ebrahimi, Mojtaba

Aging-aware Standard Cell Library Design - 09.7_6

Echeverri, Juan

Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling - 11.3_2

Echeverri, Juan Diego

Standard Cell Library Tuning for Variability Tolerant Designs - 08.7_4

Ecker, Wolfgang

The Metamodeling Approach to System Level Synthesis - 11.3_1

Eles, Petru

Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees - 03.6_2

Eles, Petru

An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs - 05.7_5

Elfadel, Ibrahim (Abe) M.

Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1

Elfadel, Ibrahim (Abe) M.

Unified, Ultra Compact, Quadratic Power Proxies for Multi-Core Processors - 11.6_6

Engelke, Piet

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1

Erb, Dominik

Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1

Ernst, Rolf

Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5

Eusse, Juan Fernando

A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2

Evans, Adrian

Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1

Evans, Adrian

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Eyole, Mbou

Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6

F

Fabrie, Sebastien

Standard Cell Library Tuning for Variability Tolerant Designs - 08.7_4

Fahrny, Jim

ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design - 04.3_1

Falk, Joachim

Model-Based Actor Multiplexing with Application to Complex Communication Protocols 08.5_4

Fan, Deliang

Brain-Inspired Computing with Spin Torque Devices - 08.8_2

Fang, B.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Farahpour, Nazanin

Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1

Farbeh, Hamed

PSP-Cache: A Low-Cost Fault-Tolerant Cache Memory Architecture - 06.7_5

Farella, Elisabetta

Context Aware Power Management for Motion-sensing Body Area Network Nodes - 07.3_3

Farhady Ghalaty, Nahid

Analyzing and Eliminating the Causes of Fault Sensitivity Analysis - 08.3_2

Farmahini-Farahani, Amin

Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4

Feng, Philip X.-L.

Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3

Feng, Tao

Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3

Ferent, Cristian

Novel Circuit Topology Synthesis Method Using Circuit Feature Mining and Symbolic Comparison - 02.4_8

Fernández, F.V.

Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits - 02.4_3

Fernández, F.V.

Model Based Hierarchical Optimization Strategies for Analog Design Automation - 02.4_5

Fernández Villena, Jorge

Efficient Analysis of Variability Impact on Interconnect Lines and Resistor Networks - 03.4_2

Ferrandi, Fabrizio

An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems - 07.4_7

Ferro, Luca

Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4

Finn, John B.

Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems 03.6_6

Firouzi, Farshad

P/G TSV Planning for IR-drop Reduction in 3D-ICs - 03.4_4

Firouzi, Farshad

Aging-aware Standard Cell Library Design - 09.7_6

Fischer, Peter

Thinfilm Printed Ferro-Electric Memories and Integrated Products - 10.1_5

Fischer, Viktor

On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models - 03.3_2

Fischer, Bernhard

Power Modeling and Analysis in Early Design Phases - 08.1_1

Fischmeister, Sebastian

Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications - 10.6_3

Flores, Paulo

Optimization of Design Complexity in Time-Multiplexed Constant Multiplications - 10.7_7

Forte, Domenic

ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design - 04.3_1

Fourmigue, Alain

Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias - 04.4_2

Fradet, Pascal

Verification-guided Voter Minimization in Triple-Modular Redundant Circuits - 04.7_2

Francillon, Aurélien

A Minimalist Approach to Remote Attestation - 09.3_2

Friedler, Ophir

Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3

Frijns, R.M.W.

Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2

Fu, Jian

A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor - 03.7_4

Fujiwara, Ikki

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Fummi, F.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2

Fummi, Franco

Moving from Co-Simulation to Simulation for Effective Smart Systems Design - 10.4_5

Fummi, Franco

Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8

Fusella, Edoardo

Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems - 11.7_5

G

Gabrielli, Giacomo

Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6

Gaillardon, Pierre-Emmanuel

Advanced System on a Chip Design Based on Controllable-Polarity FETs - 09.1_2

Gaillardon, Pierre-Emmanuel

An Efficient Manipulation Package for Biconditional Binary Decision Diagrams - 10.7_3

Gal, Raviv

ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1

Galfano, Salvatore

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3

Gallo, Luca

Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems - 11.7_5

Galzur, Ori

Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2

Ganapathy, Shrikanth

INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4

Gangopadhya, Samantak

Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3

Gao, Yue

An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems - 04.7_4

García-Ortiz, Alberto

DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs. - 11.2_4

Geilen, M.C.W.

Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2

Geilen, Marc

Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming - 11.5_3

Gemmeke, Tobias

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3

Geraci, James R.

Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5

Geng, Hui

MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2

Ghasemazar, Amin

Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions - 08.6_7

Ghiribaldi, Alberto

Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3

Gholipour, Morteza

Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3

Giannopoulou, Georgia

Mapping Mixed-Criticality Applications on Multi-Core Architectures - 05.1_3

Giannopoulou, Georgia

Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems - 07.6_2

Gimmler-Dumont, Christina

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Gines, Antonio

Sigma-Delta Testability for Pipeline A/D Converters - 12.7_4

Girault, Alain

Verification-guided Voter Minimization in Triple-Modular Redundant Circuits - 04.7_2

Gladigau, Jens

A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving - 08.5_5

Glaβ, Michael

A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3

Glaβ, Michael

Multi-Variant-based Design Space Exploration for Automotive Embedded Systems - 02.3_4

Glaβ, Michael

Multi-Objective Distributed Run-time Resource Management for Many-Cores - 08.6_3

Glaβ, Michael

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Glaβ, Michael

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1

Goens, Andrés

Optimized Buffer Allocation in Multicore Platforms - 11.5_2

Gómez Pérez, José Ignacio

Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3

Gomony, Manil Dev

Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems - 03.5_1

Goncalves, O.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

González, Antonio

INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4

Goossens, Kees

Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems - 03.5_1

Goossens, Kees

Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1

Goossens, Kees

CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4

Goossens, Sven

Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1

Goryachev, Alex

Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8

Goswami, Dip

Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3

Goyal, Ajay

The Metamodeling Approach to System Level Synthesis - 11.3_1

Graf, Sebastian

Multi-Variant-based Design Space Exploration for Automotive Embedded Systems - 02.3_4

Grani, Paolo

Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3

Gregorek, Daniel

DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs. - 11.2_4

Grijnevitch, Inna

Facilitating Timing Debug by Logic Path Correspondence - 09.7_1

Grimm, Christoph

Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1

Grimm, Christoph

Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities - 02.4_7

Grinchtein, Olga

Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP - 07.6_5

Grivet-Talocia, S.

Sensitivity-based Weighting for Passivity Enforcement of Linear Macromodels in Power Integrity Applications - 03.4_1

Gross, Kenny

Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1

Grube, Matthias

Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3

Grünewald, Armin

System Integration - The Bridge between More than Moore and More Moore - 05.8

Gu, Chuancai

Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms - 10.6_2

Guan, Nan

General and Efficient Response Time Analysis for EDF Scheduling - 09.6_3

Guan, Nan

Partitioned Mixed-Criticality Scheduling on Multiprocessor Platforms - 10.6_2

Guarnieri, V.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2

Guerre, Alexandre

A Unified Methodology for a Fast Benchmarking of Parallel Architecture - 07.6_7

Guerre, Alexandre

Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4

Guillaume-Sage, Ludovic

Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1

Güneysu, Tim

Lightweight Code-based Cryptography: QC-MDPC McEliece Encryption on Reconfigurable Devices - 03.3_1

Guo, Hui

EATBit: Effective Automated Test for Binary Translation with High Code Coverage - 04.6_1

Gupta, Rajesh K.

Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs - 05.3_1

Gupta, Sandeep K.

An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems - 04.7_4

Gurumurthi, S.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

H

Ha, Soonhoi

Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5

Ha, Yajun

Thermal-Aware Frequency Scaling for Adaptive Workloads on Heterogeneous MPSoCs - 10.6_1

Haase, Joachim

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5

Haddad, Patrick

On the Assumption of Mutual Independence of Jitter Realizations in P-Trng Stochastic Models - 03.3_2

Hahn, Kai

System Integration - The Bridge between More than Moore and More Moore - 05.8

Hairbucher, Jürgen

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Halak, Basel

A Low-Cost Radiation Hardened Flip-flop - 06.7_4

Hamdioui, Said

Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2

Hamdioui, Said

Hacking and Protecting IC Hardware - 05.2

Hamdioui, Said

Interconnect Test for 3D Stacked Memory-on-Logic - 05.7_2

Hamdioui, Said

Testing PUF-Based Secure Key Storage Circuits - 07.7_2

Han, Gang

SAFE: Security-Aware FlexRay Scheduling Engine - 02.3_5

Han, Jaehoon

Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6

Han, Jie

A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery - 04.7_5

Han, Jie

A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction - 06.7_6

Han, Seung-Soo

A Deep Learning Methodology to Proliferate Golden Signoff Timing - 09.7_4

Han, Xu

May-Happen-in-Parallel Analysis Based on Segment Graphs for Safe ESL Models - 10.5_1

Han, Yinhe

SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing - 06.4_2

Hannig, Frank

Code Generation for Embedded Heterogeneous Architectures on Android - 04.6_3

Hao, Kecheng

Equivalence Checking for Function Pipelining in Behavioral Synthesis - 06.5_3

Hardt, Wolfram

Automated System Testing Using Dynamic and Resource Restricted Clients - 11.4_6

Harrant, Manuel

Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1

Harrant, Manuel

Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3

Hartmann, Matthias

Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3

Haubelt, Christian

Model-Based Actor Multiplexing with Application to Complex Communication Protocols 08.5_4

Haubelt, Christian

A Novel Model for System-Level Decision Making with Combined ASP and SMT Solving - 08.5_5

Hayes, John P.

Fast and Accurate Computation Using Stochastic Circuits - 04.4_4

Hayes, Michael

Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5

He, Tina

Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3

He, Xin

SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing - 06.4_2

He, Ruining

EATBit: Effective Automated Test for Binary Translation with High Code Coverage - 04.6_1

He, Yanxiang

A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6

Heidmann, Nils

Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4

Heinig, Andy

System Integration - The Bridge between More than Moore and More Moore - 05.8

Heinzig, André

Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3

Helfmeier, Clemens

Physical Vulnerabilities of Physically Unclonable Functions - 12.2_5

Hellwege, Nico

Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4

Hély, David

A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4

Henkel, Jörg

dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2

Henkel, Jörg

Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7

Henkel, Jörg

Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing - 08.6_1

Henkel, Jörg

hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6

Henkel, Jörg

mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2

Henker, S.

Integrated Circuits Processing Chemical Information: Prospects and Challenges - 12.1_1

Henrichsen, Arne

Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems - 04.2_3

Henriksson, Tomas

Optimized Buffer Allocation in Multicore Platforms - 11.5_2

Hensel, Burkhard

The Energy Benefit of Level-crossing Sampling Including the Actuator's Energy Consumption - 06.3_7

Heo, Deukhyoun

Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies - 10.2_2

Herber, Christian

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Herkersdorf, Andreas

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Herkersdorf, Andreas

Distributed Cooperative Shared Last-Level Caching in Tiled Multiprocessor System on Chip - 04.5_7

Herkersdorf, Andreas

System Integration - The Bridge between More than Moore and More Moore - 05.8

Herkersdorf, Andreas

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Hess, Christopher

Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1

Hill, Stephen

Clock-Modulation Based Watermark for Protection of Embedded Processors - 03.3_3

Hiller, Matthias

Increasing the Efficiency of Syndrome Coding for PUFs with Helper Data Compression - 04.3_3

Ho, Tsung-Yi

A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips - 04.4_3

Ho, Tsung-Yi

A Thermal Resilient Integration of Many-core Microprocessors and Main Memory by 2.5D TSI I/Os - 07.4_5

Hochapfel, Erik

Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL - 08.4_2

Hoffman, Caio

Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5

Höhlein, Tim

Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4

Holcomb, Daniel E.

PUFs at a Glance - 12.2_2

Homayoun, Houman

Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design - 11.7_1

Hon, Wing-Kai

Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6

Hong, Seongsoo

Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5

Horrein, Pierre-Henri

Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL - 08.4_2

Horstmann, Manfred

Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2

Horta, Nuno

Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1

Hortváth, András

Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3

Hoskote, Yatin

Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism - 12.5_3

Hsieh, Jen-Wei

Garbage Collection for Multi-version Index on Flash Memory - 03.6_4

Hsu, Chang-Hong

ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1

Hsu, Chun-Kai

Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction - 08.7_2

Hsu, Ruei-Siang

Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5

Hu, Alan J.

Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8

Hu, X. Sharon

Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study - 05.6_2

Hu, X. Sharon

Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3

Hu, Yu

Partial-SET: Write Speedup of PCM Main Memory - 03.5_5

Huang, Ching-Yi

Rewiring for Threshold Logic Circuit Minimization - 05.6_4

Huang, Ching-Yi

Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5

Huang, Juinn-Dar

Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints - 05.6_6

Huang, Libo

Leveraging On-Chip Networks for Efficient Prediction on Multicore Coherence - 07.4_6

Huang, Pengcheng

Mapping Mixed-Criticality Applications on Multi-Core Architectures - 05.1_3

Huang, Po-Chun

Garbage Collection for Multi-version Index on Flash Memory - 03.6_4

Huang, Shih-Hsu

Leakage-Power-Aware Clock Period Minimization - 09.7_3

Huang, Zhengfeng

A High Performance SEU-Tolerant Latch for Nanoscale CMOS Technology - 06.7_3

Hum, Robert

Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2

Hum, Robert

Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2

Hwang, Hyeon I

A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4

I

Iannopollo, Antonio

Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems 03.6_6

Iannopollo, Antonio

Library-Based Scalable Refinement Checking for Contract-Based Design - 06.6_1

Ienne, Paolo

SKETCHILOG: Sketching Combinational Circuits - 06.5_5

Ienne, Paolo

Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1

Iliasov, Alex

Design of Safety Critical Systems by Refinement - 04.6_4

Imhof, Michael E.

Bit-Flipping Scan - A Unified Architecture for Fault Tolerance and Offline Test - 07.7_1

Indaco, Marco

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3

Ivanov, Radoslav

Attack-Resilient Sensor Fusion - 03.6_1

Izu, Cruz

Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs - 09.2_4

J

Jaber, K.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Jain, Arvind

Multi-Site Test Optimization for Multi-V_dd SoCs Using Space- and Time-Division Multiplexing - 05.7_4

Jaksić, Zoran

DRAM-based Coherent Caches and How to Take Advantage of the Coherence Protocol to Reduce the Refresh Energy - 04.5_5

Jalle, Javier

Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2

Jancke, Roland

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5

Jantsch, Axel

Parallel Probe Based Dynamic Connection Setup in TDM NoCs - 09.2_2

Javaid, Haris

Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs - 10.4_2

Javaid, Haris

Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs - 12.3_1

Jeong, Jae Woong

Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2

Jerke, Goeran

Mission Profile Aware IC Design - A Case Study - 03.8_2

Jesshope, Chris R.

A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor - 03.7_4

Jiang, Yingtao

Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model - 11.6_5

Jiang, Nan

A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6

Jin, Yier

Real-Time Trust Evaluation in Integrated Circuits - 04.7_1

Jin, Yier

EDA Tools Trust Evaluation through Security Property Proofs - 09.3_5

Jones, Timothy M.

ALLARM: Optimizing Sparse Directories for Thread-Local Data - 04.5_2

Jonna, Gnaneswara Rao

Minimally Buffered Single-Cycle Deflection Router - 11.2_5

Joosten, Sebastiaan J.C.

Scalable Liveness Verification for Communication Fabrics - 05.5_1

Jose, John

Minimally Buffered Single-Cycle Deflection Router - 11.2_5

Joshi, Ajay

Sub-threshold Logic Circuit Design Using Feedback Equalization - 05.4_2

Joshi, Ajay

Thermal Management of Manycore Systems with Silicon-Photonic Networks 11.2_2

Jovanovic, Natalija

Resistive Memories: Which Applications? - 10.1_4

Jung, Matthias

Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh - 10.3_6

Junsangsri, Pilin

A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction - 06.7_6

K

Kabitzsch, Klaus

The Energy Benefit of Level-crossing Sampling Including the Actuator's Energy Consumption - 06.3_7

Kaczer, Ben

Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2

Kadry, Wisam

Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3

Kagami, Takahiro

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Kahng, Andrew B.

Mission Profile Aware IC Design - A Case Study - 03.8_2

Kahng, Andrew B.

Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement - 07.7_4

Kahng, Andrew B.

A Deep Learning Methodology to Proliferate Golden Signoff Timing - 09.7_4

Kamal, Mehdi

Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions - 08.6_7

Kang, Shin-Haeng

Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5

Kang, Wang

Spintronics for Low-Power Computing - 11.1_1

Kang, Ilgweon

Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement - 07.7_4

Karakonstantis, Georgios

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4

Karam, Robert

Energy-Efficient Hardware Acceleration through Computing in the Memory - 09.8_3

Karg, S.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Karkar, Ammar

Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4

Karlsson, Christer

Thinfilm Printed Ferro-Electric Memories and Integrated Products - 10.1_5

Karri, Ramesh

Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation - 02.7_6

Karvouniari, Anna

Spatial Pattern Prediction Based Management of Faulty Data Caches - 03.7_1

Katzschke, C.

Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4

Kauer, Matthias

Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3

Kauer, Matthias

Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3

Kaule, Dirk

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Kavousianos, Xrysovalantis

Multi-Site Test Optimization for Multi-V_dd SoCs Using Space- and Time-Division Multiplexing - 05.7_4

Keramidas, Georgios

Spatial Pattern Prediction Based Management of Faulty Data Caches - 03.7_1

Kerkhoff, Hans G.

An Embedded Offset and Gain Instrument for OpAmp IPs - 02.4_9

Kerzerho, V.

New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7

Khaleghi, Behnam

A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology - 11.7_2

Khan, Muhammad Usman Karim

Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing - 08.6_1

Khan, Seyab

Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2

Khdr, Heba

mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2

Kiamehr, Saman

Aging-aware Standard Cell Library Design - 09.7_6

Kim, BaekGyu

A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4

Kim, Chris H.

Improving STT-MRAM Density through Multibit Error Correction - 07.5_3

Kim, Dongyoung

Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3

Kim, Geunho

Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs - 09.7_8

Kim, Hayoung

Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3

Kim, Jae-Joon

Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3

Kim, Jay

Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6

Kim, John

Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1

Kim, Jongyeon

Improving STT-MRAM Density through Multibit Error Correction - 07.5_3

Kim, Jungsoo

Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1

Kim, Kibeom

Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5

Kim, Kitae

FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4

Kim, Moon Seok

Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2

Kim, Myungsun

Utilization-aware Load Balancing for the Energy Efficient Operation on the big.LITTLE Processor - 08.6_5

Kim, Namdo

Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6

Kim, Nam Sung

Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4

Kim, Ryan

Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies - 10.2_2

Kim, Sungchan

Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality - 11.5_5

Kim, Taemin

Automatic Generation of Custom SIMD Instructions for Superword Level Parallelism - 12.5_3

Kim, Taewhan

Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs - 09.7_8

Kirscher, Jérôme

Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1

Klauk, Hagen

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Kleeberger, Veit B.

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Klein, Jacques-Olivier

Spintronics for Low-Power Computing - 11.1_1

Kobyashi, Hiroaki

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Koedam, Martijn

Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization - 07.4_1

Koedam, Martijn

CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4

Koibuchi, Michihiro

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Komalan, Manu

Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3

Komoda, Toshiya

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Kondo, Masaaki

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Kong, Pingfan

Energy Efficient In-Memory AES Encryption Based on Nonvolatile Domain-wall Nanowire - 07.5_4

König, Markus

Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3

Könighofer, Robert

Partial Witnesses from Preprocessed Quantified Boolean Formulas - 06.5_2

Kordes, Alexander

Startup Error Detection and Containment to Improve the Robustness of Hybrid FlexRay Networks - 02.3_2

Kosmidis, Leonidas

Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2

Koundinya, Pranav

Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3

Koushanfar, Farinaz

D2Cyber: A Design Automation Tool for Dependable Cybercars - 03.6_5

Koushanfar, Farinaz

Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder Based Security - 12.2_7

Kraft, Ulrike

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Kress, Rainer

Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2

Kreupl, Franz

Advancing CMOS with Carbon Electronics - 09.1_4

Kröhnert, Steffen

System Integration - The Bridge between More than Moore and More Moore - 05.8

Kriebel, Florian

Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7

Kuehlmann, Andreas

Property Directed Invariant Refinement for Program Verification - 05.5_2

Kudo, Masaru

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Kufel, Jedrzej

Clock-Modulation Based Watermark for Protection of Embedded Processors - 03.3_3

Kukner, Halil

Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2

Kumar, A.

Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs - 03.7_2

Kumar, Akash

Temperature Aware Energy-Reliability Trade-offs for Mapping of Throughput-Constrained Applications on Multimedia MPSoCs - 05.3_3

Kumar, Pratyush

Computing a Language-Based Guarantee for Timing Properties of Cyber-Physical Systems - 07.6_2

Kumar, Pratyush

COOLIP: Simple yet Effective Job Allocation for Distributed Thermally-Throttled Processors - 10.3_5

Kuroda, Tadahiro

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Kwak, Doowhan

Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6

L

Lager, Guillaume

Time-Critical Computing on a Single Chip Massively Parallel Processor - 05.1_2

Lagraa, Sofiane

Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces - 07.6_1

Lai, Kuan-Yu

Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6

Lam, Kam-Yiu

Garbage Collection for Multi-version Index on Flash Memory - 03.6_4

Lange, André

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5

Larsson-Edefors, Per

Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD³) - 04.5_6

Lauer, Christoph

Multi-Variant-based Design Space Exploration for Automotive Embedded Systems - 02.3_4

Lauwereins, Rudy

Interfacing to Living Cells - 12.1_2

Layer, C.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Le Beux, Sébastien

CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2

Le, Hoang M.

Towards Verifying Determinism of SystemC Designs - 06.5_6

Le Nours, Sébastien

A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures 10.5_3

Lee, Chia-Yi

Design-for-Debug Routing for FIB Probing - 11.4_4

Lee, Doowon

Brisk and Limited-Impact NoC Routing Reconfiguration - 11.2_1

Lee, Haeseung

GPU-EvR: Run-time Event Based Real-time Scheduling Framework on GPGPU Platform - 08.6_2

Lee, Hsun-Cheng

A Novel Low Power 11-bit Hybrid ADC Using Flash and Delay Line Architectures - 02.4_6

Lee, Insup

Attack-Resilient Sensor Fusion - 03.6_1

Lee, Insup

A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4

Lee, Jungseob

Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4

Lee, Ming-Chao

Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6

Lee, Minseok

Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1

Lee, Sunggu

Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation - 06.6_6

Lee, Sunggu

Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs - 12.6_3

Lee, Young-Joon

On GPU Bus Power Reduction with 3D IC Technologies - 07.4_3

Lee, Youngtak

Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3

Lee, Woojoo

VRCon: Dynamic Reconfiguration of Voltage Regulators in a Multicore Platform - 12.6_2

Leeser, Miriam

Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic - 05.5_5

Leger, Gildas

Sigma-Delta Testability for Pipeline A/D Converters - 12.7_4

Lei, Li

Coverage Evaluation of Post-silicon Validation Tests with Virtual Prototypes - 11.4_2

Leibe, Bastian

A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2

Leo, K.

Organic Electronics - From Lab to Markets - 11.0

Letzkus, Florian

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Leupers, Rainer

Technology Transfer towards Horizon 2020 - 02.8

Leupers, Rainer

Time-Decoupled Parallel SystemC Simulation - 07.6_6

Leupers, Rainer

Automatic Detection of Concurrency Bugs through Event Ordering Constraints - 10.4_1

Leupers, Rainer

Optimized Buffer Allocation in Multicore Platforms - 11.5_2

Leupers, Rainer

A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2

Leveugle, Régis

A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4

Levitan, Steve

Video Analytics Using Beyond CMOS Devices - 12.1_3

Lhuillier, Yves

A Unified Methodology for a Fast Benchmarking of Parallel Architecture - 07.6_7

Li, Bing

Partial-SET: Write Speedup of PCM Main Memory - 03.5_5

Li, Boxun

ICE: Inline Calibration for Memristor Crossbar-based Computing Engine - 07.5_5

Li, Boxun

Energy Efficient Neural Networks for Big Data Analytics - 12.1_4

Li, Hai (Helen)

ICE: Inline Calibration for Memristor Crossbar-based Computing Engine - 07.5_5

Li, Helen

Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation - 06.6_6

Li, Huawei

Functional Test Generation Guided by Steady-State Probabilities of Abstract Design - 11.4_5

Li, Hui

CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2

Li, Jiayin

Write-Once-Memory-Code Phase Change Memory - 07.5_2

Li, Min

Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5

Li, Qingan

A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems - 04.6_6

Li, Tai-Hung

Design-for-Debug Routing for FIB Probing - 11.4_4

Li, Xiaowei

Partial-SET: Write Speedup of PCM Main Memory - 03.5_5

Li, Xiaowei

SuperRange: Wide Operational Range Power Delivery Design for Both STV and NTV Computing - 06.4_2

Li, Xiaowei

Functional Test Generation Guided by Steady-State Probabilities of Abstract Design - 11.4_5

Li, Yaping

SAFE: Security-Aware FlexRay Scheduling Engine - 02.3_5

Li, Yueting

ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits - 12.5_2

Li, Zhen

A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6

Liang, Yun

WCET-Centric Dynamic Instruction Cache Locking - 02.6_2

Lilja, David J.

IIR Filters Using Stochastic Arithmetic - 04.4_1

Lim, Sung Kyu

On GPU Bus Power Reduction with 3D IC Technologies - 07.4_3

Lin, Chia-Chun

Rewiring for Threshold Logic Circuit Minimization - 05.6_4

Lin, Fan

Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction - 08.7_2

Lin, Hsin-Chang

Mask-Cost-Aware ECO Routing - 03.4_8

Lin, Hsueh-Ju

Package Geometric Aware Thermal Analysis by Infrared-Radiation Thermal Images - 03.4_5

Lin, Xue

Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles - 05.4_4

Lin, Yang

A Low-Cost Radiation Hardened Flip-flop - 06.7_4

Lin, Zhiqiang

Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy - 03.5_3

Lippmann, Mirko

Automated System Testing Using Dynamic and Resource Restricted Clients - 11.4_6

Liu, Bao

Embedded Reconfigurable Logic for ASIC Design Obfuscation against Supply Chain Attacks - 09.3_1

Liu, Chian-Wei

Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5

Liu, Cong

A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery - 04.7_5

Liu, Di

Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3

Liu, Jianming

MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2

Liu, Jianxiong

Image Progressive Acquisition for Hardware Systems - 12.3_3

Liu, Leibo

Extending Lifetime of Battery-Powered Coarse-Grained Reconfigurable Computing Platforms - 11.7_3

Liu, Shaoteng

Parallel Probe Based Dynamic Connection Setup in TDM NoCs - 09.2_2

Liu, Wen-Hao

Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost - 12.4_3

Liu, Xuchen

CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2

Liu, Ziyi

Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy - 03.5_3

Lo, Paul

Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2

Loi, Igor

A Multi Banked - Multi Ported - non Blocking Shared L2 Cache for MPSoC Platforms 04.5_4

Lombardi, Fabrizio

A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery - 04.7_5

Lombardi, Fabrizio

A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction - 06.7_6

Long, Yanchen

Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models - 09.4_4

Lora, Michele

Moving from Co-Simulation to Simulation for Effective Smart Systems Design - 10.4_5

Lorenz, Ingolf

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5

Lourenço, Nuno

Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1

Lu, Tianyue

Achieving Efficient Packet-based Memory System by Exploiting Correlation of Memory Requests - 04.5_1

Lu, Youyou

p-OFTL: An Object-based Semantic-aware Parallel Flash Translation Layer - 06.6_4

Lu, Zhonghai

Parallel Probe Based Dynamic Connection Setup in TDM NoCs - 09.2_2

Lu, Zhonghai

Empowering Study of Delay Bound Tightness with Simulated Annealing - 09.4_3

Lu, Zhonghai

Analysis and Evaluation of Per-Flow Delay Bound for Multiplexing Models - 09.4_4

Lübbers, Enno

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Lukasiewycz, Martin

Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3

Luo, Rong

Energy Efficient Neural Networks for Big Data Analytics - 12.1_4

Lv, Tao

Functional Test Generation Guided by Steady-State Probabilities of Abstract Design - 11.4_5

M

M, Vijaykumar,

Statistical Static Timing Analysis Using a Skew-Normal Canonical Delay Model - 09.7_2

Macii, E.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2

Macii, Enrico

Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache - 07.4_2

Macii, Enrico

Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits - 09.7_7

Macii, Enrico

Thermal Management of Batteries Using a Hybrid Supercapacitor Architecture - 11.6_3

Macrelli, Enrico

Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5

Magarshack, Philippe

Panel: Emerging vs. Established Technologies: A Two Sphinxes' Riddle at the Crossroads? - 02.2

Mahmood, Haroon

Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache - 07.4_2

Mahmoodi, Hamid

Exploiting STT-NV Technology for Reconfigurable, High Performance, Low Power, and Low Temperature Functional Unit Design - 11.7_1

Mai, Ken

An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS - 04.3_2

Maistri, Paolo

A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4

Mak, Terrence

Hybrid Wire-Surface Wave Architecture for One-to-Many Communication in Network-on-Chip - 10.2_4

Mak, Terrence

Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model - 11.6_5

Makris, Yiorgos

An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions - 12.7_1

Maliuk, Dzmitry

An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions - 12.7_1

Maniatakos, Michail

HEROIC: Homomorphically EncRypted One Instruction Computer - 09.3_4

Marculescu, Radu

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Mariani, Giovanni

DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling - 08.5_6

Marinissen, Erik Jan

Interconnect Test for 3D Stacked Memory-on-Logic - 05.7_2

Marongiu, Andrea

A Tightly-coupled Hardware Controller to Improve Scalability and Programmability of Shared-Memory Heterogeneous Clusters - 02.5_7

Marongiu, Andrea

Tightly-Coupled Hardware Support to Dynamic Parallelism Acceleration in Embedded Shared Memory Clusters - 06.6_3

Martins, Ricardo

Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures - 02.4_1

Masadeh, Mahmoud

Interconnect Test for 3D Stacked Memory-on-Logic - 05.7_2

Masrur, Alejandro

The Schedulability Region of Two-Level Mixed-Criticality Systems Based on EDF-VD - 09.6_4

Mathew, Jimson

A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6

Mathew, Jimson

Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication - 07.5_6

Matsunaga, Kensaku

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Matsunaga, Yusuke

Synthesis Algorithm of Parallel Index Generation Units - 10.7_4

Matsutani, Hiroki

Low-Latency Wireless 3D NoCs via Randomized Shortcut Chips - 10.2_3

Mattheakis, P.

Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8

Maurer, Peter M.

A Universal Symmetry Detection Algorithm - 10.7_6

Maurine, Philippe

Efficiency of a Glitch Detector against Electromagnetic Fault Injection - 08.3_1

Mavropoulos, Michail

Spatial Pattern Prediction Based Management of Faulty Data Caches - 03.7_1

Mazzeo, Antonino

Joint Communication Scheduling and Interconnect Synthesis for FPGA-based Many-Core Systems - 11.7_5

Meeus, Wim

Automating Data Reuse in High-Level Synthesis - 10.7_5

Meguerdichian, Saro

Provably Minimal Energy Using Coordinated DVS and Power Gating - 10.7_1

Mehregany, Mehran

Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3

Meijer, Maurice

Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling - 11.3_2

Membarth, Richard

Code Generation for Embedded Heterogeneous Architectures on Android - 04.6_3

Mena Morales, Valentin

Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL - 08.4_2

Mensch, P.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Mera, Maria Isabel

Trade-offs in Execution Signature Compression for Reliable Processor Systems - 04.7_3

Mercati, Pietro

A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5

Meyer, Brett H.

Trade-offs in Execution Signature Compression for Reliable Processor Systems - 04.7_3

Meyer zu Bexten, V.

Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4

Michel, Bruno

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2

Michel, Hans Ulrich

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Micheloni, Rino

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3

Miele, A.

Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs - 03.7_2

Mikolajick, Thomas

Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges - 09.1_3

Milder, Peter

Trade-offs in Execution Signature Compression for Reliable Processor Systems - 04.7_3

Miller, Felix

System Integration - The Bridge between More than Moore and More Moore - 05.8

Minematsu, Kazuhiko

A Smaller and Faster Variant of RSM - 08.3_3

Mineo, Andrea,

An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs - 10.2_1

Miremadi, Seyed Ghassem

PSP-Cache: A Low-Cost Fault-Tolerant Cache Memory Architecture - 06.7_5

Mitra, Tulika

WCET-Centric Dynamic Instruction Cache Locking - 02.6_2

Mohanram, Kartik

Write-Once-Memory-Code Phase Change Memory - 07.5_2

Mokhov, Andrey

Design of Safety Critical Systems by Refinement - 04.6_4

Molnos, Anca

CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4

Monteiro, José

Optimization of Design Complexity in Time-Multiplexed Constant Multiplications - 10.7_7

Moore, Ryan W.

Program Affinity Performance Models for Performance and Utilization - 02.5_5

Morad, Ronny

ArChiVED: Architectural Checking via Event Digests for High Performance Validation - 11.4_1

Morad, Ronny

Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8

Moreira, Orlando

Mode-Controlled Dataflow Based Modeling & Analysis of a 4G-LTE Receiver - 08.4_6

Moreno, Javier

Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities - 02.4_7

Morgenshtein, Arkadiy

Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3

Morrow, Katherine

Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4

Moselund, K.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Mottaghi, Mohammad D.

RETLab: A Fast Design-automation Framework for Arbitrary RET Networks - 05.6_1

Muhr, Hannes

Power Modeling and Analysis in Early Design Phases - 08.1_1

Mukherjee, Saoni

Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic - 05.5_5

Mukhopadhyay, Saibal

Ultra-low Power Electronics with Si/Ge Tunnel FET - 08.8_1

Müller, Dirk

The Schedulability Region of Two-Level Mixed-Criticality Systems Based on EDF-VD - 09.6_4

Munir, Arslan

D2Cyber: A Design Automation Tool for Dependable Cybercars - 03.6_5

Murali Krishna, G.

EDT: A Specification Notation for Reactive Systems - 08.5_3

Murillo, Luis Gabriel

Automatic Detection of Concurrency Bugs through Event Ordering Constraints - 10.4_1

Murmann, Boris

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Murray, Jacob

Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies - 10.2_2

Mutyam, Madhu

Minimally Buffered Single-Cycle Deflection Router - 11.2_5

Myers, James

Clock-Modulation Based Watermark for Protection of Embedded Processors - 03.3_3

N

Nahas, Joseph

Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study - 05.6_2

Nahas, Joseph

Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3

Nahir, Amir

Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3

Nakamura, Hiroshi

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Namiki, Mitaro

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Naqvi, Syed Rameez

A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments - 10.7_2

Narayan, Sanjiv

Energy Optimization in Android Applications through Wakelock Placement - 04.6_5

Narayanan, Vijaykrishnan

Width Minimization in the Single-Electron Transistor Array Synthesis - 05.6_5

Narayanan, V.

Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2

Narayanan, Vijaykrishnan

Video Analytics Using Beyond CMOS Devices - 12.1_3

Narayanaswamy, Swaminathan

Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3

Nassif, Sani R.

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Natarajan, Vishwanath

Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2

Nath, Siddhartha

A Deep Learning Methodology to Proliferate Golden Signoff Timing - 09.7_4

Nathan, Ralph

Nostradamus: Low-Cost Hardware-Only Error Detection for Processor Cores - 06.7_1

Nawinne, Isuru

Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs - 10.4_2

Nedospasov, Dmitry

Physical Vulnerabilities of Physically Unclonable Functions - 12.2_5

Nejat, Mehrzad

Dynamic Flip-Flop Conversion to Tolerate Process Variation in Low Power Circuits - 05.4_5

Nelson, Andrew

CoMik: A Predictable and Cycle-Accurately Composable Real-Time Microkernel - 08.6_4

Nemoto, Kae

Software-based Pauli Tracking in Fault-tolerant Quantum Circuits - 05.6_7

Nepal, Kumud

ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits - 12.5_2

Nguyen, Quan

A Minimalist Approach to Remote Attestation - 09.3_2

Nicolescu, Gabriela

Efficient Transient Thermal Simulation of 3D ICs with Liquid-Cooling and Through Silicon Vias - 04.4_2

Nicolescu, Gabriela

CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2

Nicopoulos, C.

ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers - 09.2_3

Nieh, Yow-Tyng

Leakage-Power-Aware Clock Period Minimization - 09.7_3

Niemier, Michael

Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study - 05.6_2

Niemier, Michael

Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3

Nikitakis, Antonis

A Novel Embedded System for Vision Tracking - 11.7_6

Nikolos, Dimitris

Spatial Pattern Prediction Based Management of Faulty Data Caches - 03.7_1

Nirmaier, Thomas

Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1

Nirmaier, Thomas

Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3

Novo, David

SKETCHILOG: Sketching Combinational Circuits - 06.5_5

Novo, David

Energy Efficient MIMO Processing: A Case Study of Opportunistic Run-Time Approximations - 08.4_1

Nowotsch, Jan

Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems - 04.2_3

Nozieres, J.P.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Nuzzo, Pierluigi

Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems 03.6_6

Nuzzo, Pierluigi

Library-Based Scalable Refinement Checking for Contract-Based Design - 06.6_1

O

Öberg, Johnny

From Simulink to NoC-based MPSoC on FPGA - 11.5_6

Oboril, Fabian

P/G TSV Planning for IR-drop Reduction in 3D-ICs - 03.4_4

Oboril, Fabian

Asynchronous Asymmetrical Write Termination (AAWT) for a Low Power STT-MRAM - 07.5_1

Connor, Ian O'

CHAMELEON: CHANNEL Efficient Optical Network-on-Chip - 11.1_2

Odendahl, Maximilian

Optimized Buffer Allocation in Multicore Platforms - 11.5_2

Okamura, Toshihiko

A Smaller and Faster Variant of RSM - 08.3_3

Olbrich, M.

Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4

Olivo, Pirero

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3

Onkaraiah, Santhosh

Resistive Memories: Which Applications? - 10.1_4

Orailoglu, Alex

On-Device Objective-C Application Optimization Framework for High-Performance Mobile Processors - 04.6_2

Ortín, Marta

Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs - 09.2_4

Osewold, Christof

DCM: An IP for the Autonomous Control of Optical and Electrical Reconfigurable NoCs. - 11.2_4

Ottavi, Marco

Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication - 07.5_6

Oucheikh, Houcine

Resistive Memories: Which Applications? - 10.1_4

Ouyang, Peng

Extending Lifetime of Battery-Powered Coarse-Grained Reconfigurable Computing Platforms - 11.7_3

Ozev, Sule

Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation - 02.7_6

Ozev, Sule

Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2

P

Paganelli, Rudi Paolo

Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5

Paganos, Theofilos

A Novel Embedded System for Vision Tracking - 11.7_6

Pajic, Miroslav

Attack-Resilient Sensor Fusion - 03.6_1

Paler, Alexandru

Software-based Pauli Tracking in Fault-tolerant Quantum Circuits - 05.6_7

Palermo, Gianluca

Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon - 08.2_2

Palermo, Gianluca

DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling - 08.5_6

Palesi, Maurizio

An Adaptive Transmitting Power Technique for Energy Efficient mm-Wave Wireless NoCs - 10.2_1

Palesi, Maurizio

Adaptive Power Allocation for Many-core Systems Inspired from Multiagent Auction Model - 11.6_5

Palit, Indranil

Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3

Palella, Pietro

Panel: The World Is Going... Analog & Mixed-Signal! What about EDA? - 03.2

Palomar, Oscar

EVX: Vector Execution on Low Power EDGE Cores - 02.5_4

Palomino, Daniel

hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6

Pan, Xiao

Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities - 02.4_7

Panda, Biswabandan

Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control - 04.5_3

Panda, Preeti Ranjan

Energy Optimization in Android Applications through Wakelock Placement - 04.6_5

Panda, Preeti Ranjan

Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5

Pande, Partha Pratim

Performance Evaluation of Wireless NoCs in Presence of Irregular Network Routing Strategies - 10.2_2

Pandey, Sujan

Transient Errors Resiliency Analysis Technique for Automotive Safety Critical Applications - 02.3_6

Papachristou, Christos

Cross-correlation of Specification and RTL for Soft IP Analysis - 10.5_4

Papadimitriou, Athanasios

A Multiple Fault Injection Methodology Based on Cone Partitioning towards RTL Modeling of Laser Attacks - 08.3_4

Papaefstathiou, Ioannis

A Novel Embedded System for Vision Tracking - 11.7_6

Parameswaran, Sri

Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs - 10.4_2

Parameswaran, Sri

Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs - 12.3_1

Parekhji, Rubin

Multi-Site Test Optimization for Multi-V_dd SoCs Using Space- and Time-Division Multiplexing - 05.7_4

Parikh, Ritesh

Brisk and Limited-Impact NoC Routing Reconfiguration - 11.2_1

Park, Eunhyek

Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation - 06.6_6

Park, Junhyuck

Predictive Parallel Event-driven HDL Simulation with A New Powerful Prediction Strategy - 11.3_6

Park, Kitae

Mixed Allocation of Adjustable Delay Buffers Combined with Buffer Sizing in Clock Tree Synthesis of Multiple Power Mode Designs - 09.7_8

Park, Taejoon

A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4

Pasini, P.

Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization - 05.5_4

Paterna, Francesco

A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5

Paterna, Francesco

Ambient Variation-tolerant and Inter Components Aware Thermal Management for Mobile System on Chips - 08.4_4

Pattabiraman, K.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Paul, Somnath

Energy-Efficient Hardware Acceleration through Computing in the Memory - 09.8_3

Paul, Steffen

Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4

Paulitsch, Michael

Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems - 04.2_3

P.D., Sai Manoj

Zonotope-based Nonlinear Model Order Reduction for Fast Performance Bound Analysis of Analog Circuits with Multiple-interval-valued Parameter Variations - 02.4_2

P. D., Sai Manoj

A Thermal Resilient Integration of Many-core Microprocessors and Main Memory by 2.5D TSI I/Os - 07.4_5

Pearson, Justin

Model-based Protocol Log Generation for Testing a Telecommunication Test Harness Using CLP - 07.6_5

Pedram, Massoud

An Energy-Aware Fault Tolerant Scheduling Framework for Soft Error Resilient Cloud Computing Systems - 04.7_4

Pedram, Massoud

Minimizing State-of-Health Degradation in Hybrid Electrical Energy Storage Systems with Arbitrary Source and Load Profiles - 05.4_4

Pedram, Massoud

Optimal Design and Management of a Smart Residential PV and Energy Storage System - 06.3_4

Pedram, Massoud

Improving Efficiency of Extensible Processors by Using Approximate Custom Instructions - 08.6_7

Pedram, Massoud

Application Mapping for Express Channel-Based Networks-on-Chip - 09.2_1

Pedram, Massoud

Concurrent Placement, Capacity Provisioning, and Request Flow Control for a Distributed Cloud Infrastructure - 10.3_4

Pedram, Massoud

VRCon: Dynamic Reconfiguration of Voltage Regulators in a Multicore Platform - 12.6_2

Pedram, Massoud

FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4

Pellizzoni, Rodolfo

Time-predictable Execution of Multithreaded Applications on Multicore Systems - 02.6_4

Pellizzoni, Rodolfo

Generation of Communication Schedules for Multi-Mode Distributed Real-Time Applications - 10.6_3

Peltier, Nicolas

Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4

Pelz, Georg

Emulation-Based Robustness Assessment for Automotive Smart-Power ICs - 02.3_1

Pelz, Georg

Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3

Peng, Zebo

Bandwidth-Efficient Controller-Server Co-Design with Stability Guarantees - 03.6_2

Peng, Zebo

An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs - 05.7_5

Peng, Zhen-Yu

Mask-Cost-Aware ECO Routing - 03.4_8

Perricone, Robert

Design of 3D Nanomagnetic Logic Circuits: A Full-Adder Case Study - 05.6_2

Perricone, Robert

Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2

Peters-Drolshagen, Dagmar

Modeling of an Analog Recording System Design for ECoG and AP Signals - 02.4_4

Petricca, M.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2

Pétrot, Frédéric

Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces - 07.6_1

Pigorsch, Florian

Simple Interpolants for Linear Arithmetic - 05.5_3

Pineda de Gyvez, José

Standard Cell Library Tuning for Variability Tolerant Designs - 08.7_4

Pineda de Gyvez, Jose

Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling - 11.3_2

Polian, Ilia

Software-based Pauli Tracking in Fault-tolerant Quantum Circuits - 05.6_7

Pomeranz, Irith

Test and Non-Test Cubes for Diagnostic Test Generation Based on Merging of Test Cubes - 05.7_6

Pomeranz, Irith

Substituting Transition Faults with Path Delay Faults as a Basic Delay Fault Model - 08.7_3

Poncino, M.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2

Poncino, Massimo

Cache Aging Reduction with Improved Performance Using Dynamically Re-sizable Cache - 07.4_2

Poncino, Massimo

Pass-XNOR Logic: A New Logic Style for P-N Junction Based Graphene Circuits - 09.7_7

Poncino, Massimo

Thermal Management of Batteries Using a Hybrid Supercapacitor Architecture - 11.6_3

Pongratz, Werner

Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems - 04.2_3

Pontarelli, Salvatore

Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication - 07.5_6

Poon, Chung Keung

Garbage Collection for Multi-version Index on Flash Memory - 03.6_4

Portal, Jean-Michel

Resistive Memories: Which Applications? - 10.1_4

Poss, Raphael

A Fault Detection Mechanism in a Data-flow Scheduled Multithreaded Processor - 03.7_4

Postula, Adam

A Dynamic Computation Method for Fast and Accurate Performance Evaluation of Multi-core Architectures 10.5_3

Potkonjak, Miodrag

Provably Minimal Energy Using Coordinated DVS and Power Gating - 10.7_1

Potkonjak, Miodrag

Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder Based Security - 12.2_7

Potter, John

Making it Harder to Unlock an LSIB: Honeytraps and Misdirection in a P1687 Network - 07.7_3

Poulhiès, Marc

Time-Critical Computing on a Single Chip Massively Parallel Processor - 05.1_2

Pradhan, Dhiraj K.

A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6

Pradhan, Dhiraj K

Complementary Resistive Switch Based Stateful Logic Operations Using Material Implication - 07.5_6

Prakash, Varun

Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3

Prejbeanu, I.L.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Prenat, G.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Prinetto, Paolo

SSDExplorer: A Virtual Platform for Fine-Grained Design Space Exploration of Solid State Drives - 10.4_3

Psarras, A.

ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers - 09.2_3

Psarras, A. ,

Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8

Pu, Yu

Logic Synthesis of Low-power ICs with Ultra-wide Voltage and Frequency Scaling - 11.3_2

Puri, Ruchir

Energy-Efficient Hardware Acceleration through Computing in the Memory - 09.8_3

Q

Qi, Ji

Efficient Simulation and Modelling of Non-rectangular NoC Topologies - 10.4_4

Qiu, Qinru

Battery Aware Stochastic QoS Boosting in Mobile Computing Devices - 07.3_5

Qiu, Qinru

Contention Aware Frequency Scaling on CMPs with Guaranteed Quality of Service - 10.3_3

Quer, S.

Tightening BDD-based Approximate Reachability with SAT-based Clause Generalization - 05.5_4

Querlioz, Damien

Spintronics for Low-Power Computing - 11.1_1

Quiñones, Eduardo

Bus Designs for Time-Probabilistic Multicore Processors - 03.5_2

R

Radhakrishnan, Rachana

Minimally Buffered Single-Cycle Deflection Router - 11.2_5

Radojicic, Carna

Semi-Symbolic Analysis of Mixed-Signal Systems Including Discontinuities - 02.4_7

Raghavan, Praveen

Feasibility Exploration of NVM Based I-Cache through MSHR Enhancements - 02.5_3

Raghavan, Praveen

Bias Temperature Instability Analysis of FinFET Based SRAM Cells - 02.7_2

Raghavan, Praveen

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3

Raghunathan, Anand

ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1

Raha, Arnab

ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1

Rahimi, Abbas

Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPUs - 05.3_1

Rahman, Md. Tauhidur

ARO-PUF: An Aging-Resistant Ring Oscillator PUF Design - 04.3_1

Rajgopal, Srihari

Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3

Rallapalli, Arjun

RETLab: A Fast Design-automation Framework for Arbitrary RET Networks - 05.6_1

Ramachandran, Jaideep

Make it Real: Effective Floating-Point Reasoning via Exact Arithmetic - 05.5_5

Rambo, Eberle A

Failure Analysis of a Network-on-Chip for Real-Time Mixed-Critical Systems - 10.2_5

Ramini, Luca

Assessing the Energy Break-Even Point between an Optical NoC Architecture and an Aggressive Electronic Baseline 11.2_3

Ramos, Luiz

Wear-out Analysis of Error Correction Techniques in Phase-change Memory - 02.7_5

Rana, Manish

SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis - 02.7_3

Ranganathan, Vaishnavi

Toward Ultralow-Power Computing at Exteme with Silicon Carbide (SiC) Nanoelectromechanical Logic - 08.8_3

Ranjan, Ashish

ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1

Rasmussen, Kasper B.

A Minimalist Approach to Remote Attestation - 09.3_2

Ravelosona, Dafiné

Spintronics for Low-Power Computing - 11.1_1

Ray, Sandip

Equivalence Checking for Function Pipelining in Behavioral Synthesis - 06.5_3

Raychowdhury, Arijit

Modeling and Analysis of Digital Linear Dropout Regulators with Adaptive Control for High Efficiency under Wide Dynamic Range Digital Loads - 06.4_3

Rebernak, William

A Flexible BIST Strategy for SDR Transmitters - 12.7_3

Rech, P.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Reda, Sherief

ABACUS: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits - 12.5_2

Rehman, Semeen

Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7

Reiche, Oliver

Code Generation for Embedded Heterogeneous Architectures on Android - 04.6_3

Reid Alastair,

Advanced SIMD: Extending the Reach of Contemporary SIMD Architectures - 02.5_6

Reimann, Felix

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1

Reimer, Sven

Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1

Reineke, Jan

Impact of Resource Sharing on Performance and Performance Prediction - 05.1_1

Reisinger, Jochen

System Integration - The Bridge between More than Moore and More Moore - 05.8

Renovell, M.

New Implementions of Predictive Alternate Analog/RF test with Augmented Model Redundancy - 05.7_7

Richter, A.

Integrated Circuits Processing Chemical Information: Prospects and Challenges - 12.1_1

Richter, Andre

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Richter, Harald

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Richter, Jan H.

Multi-Disciplinary Integrated Design Automation Tool for Automotive Cyber-Physical Systems - 11.3_5

Riedel, Marc D.

IIR Filters Using Stochastic Arithmetic - 04.4_1

Riefert, Andreas

An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3

Riel, H.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Ries, Benjamin

Optimized Buffer Allocation in Multicore Platforms - 11.5_2

Robino, Francesco

From Simulink to NoC-based MPSoC on FPGA - 11.5_6

Roca, E.

Implementation Issues in the Hierarchical Composition of Performance Models of Analog Circuits - 02.4_3

Rödel, Reinhold

Low-Voltage Organic Transistors for Flexible Electronics - 11.1_3

Rodríguez, M. Andrea

Signature Indexing of Design Layouts for Hotspot Detection - 12.4_2

Rodríguez Gómez, Laura

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1

Roelofs, Gijs

Testing PUF-Based Secure Key Storage Circuits - 07.7_2

Romani, Aldo

Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5

Rosenstiel, Wolfgang

Mission Profile Aware Robustness Assessment of Automotive Power Devices - 03.8_3

Rosing, Tajana

Providing Regulation Services and Managing Data Center Peak Power Budgets - 06.3_6

Rosing, Tajana Simunic

Ambient Variation-tolerant and Inter Components Aware Thermal Management for Mobile System on Chips - 08.4_4

Rossi, Maurizio

Real-time Optimization of the Battery Banks Lifetime in Hybrid Residential Electrical Systems - 06.3_2

Rossi, Davide

Hybrid Memory Architecture for Voltage Scaling in Ultra-Low Power Multi-Core Biomedical Processors - 07.3_2

Rostami, Masoud

Quo Vadis, PUF? Trends and Challenges of Emerging Physical-Disorder Based Security - 12.2_7

Rosvall, Kathrin

A Constraint-Based Design Space Exploration Framework for Real-Time Applications on MPSoCs - 11.5_4

Roy, Amitabha

ALLARM: Optimizing Sparse Directories for Thread-Local Data - 04.5_2

Roy, Kaushik

Brain-Inspired Computing with Spin Torque Devices - 08.8_2

Roy, Kaushik

ASLAN: Synthesis of Approximate Sequential Circuits - 12.6_1

Roy, Saibal

Design and Fabrication of a 315 μH Bondwire Micro-Transformer for Ultra-Low Voltage Energy Harvesting - 06.3_5

Roy, Sanghamitra

DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors - 03.7_3

Rozeau, Olivier

3D FPGA Using High-density Interconnect Monolithic Integration - 11.7_4

Rubio, Antonio

INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis - 02.7_4

Ruch, Patrick

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2

Rührmair, Ulrich

Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks - 12.2_1

Rührmair, Ulrich

PUFs at a Glance - 12.2_2

Rührmair, Ulrich

PUF Modeling Attacks: An Introduction and Overview - 12.2_3

Rührmair, Ulrich

Protocol Attacks on Advanced PUF Protocols and Countermeasures - 12.2_6

Russ, Thomas

Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures - 12.5_1

Ryu, Soojung

Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1

S

Sabry, Mohamed M.

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2

Sabry, Mohamed M.

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4

Sabry, Mohamed M.

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3

Sabry, Mohamed M.

Global Fan Speed Control Considering Non-Ideal Temperature Measurements in Enterprise Servers - 10.3_1

Sadasue, Tamon

A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2

Sadri, Mohammadsadegh

Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-wise Refresh - 10.3_6

Sakamoto, Ryuichi

Design and Evaluation of Fine-Grained Power-Gating for Embedded Microprocessors - 06.4_1

Salunkhe, Hrishikesh

Mode-Controlled Dataflow Based Modeling & Analysis of a 4G-LTE Receiver - 08.4_6

Sampaio, Felipe

dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2

Sampson, Jack

Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2

Sander, Ingo

A Constraint-Based Design Space Exploration Framework for Real-Time Applications on MPSoCs - 11.5_4

Sander, Oliver

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Sandionigi, Chiara

Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4

Sandmann, Timo

Hardware Virtualization Support for Shared Resources in Mixed-Criticality Multicore Systems - 04.2_4

Sangai, Amit

Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling - 05.6_3

Sangiovanni-Vincentelli, Alberto L.

Contract-Based Design of Control Protocols for Safety-Critical Cyber-Physical Systems 03.6_6

Sangiovanni-Vincentelli, Alberto

Library-Based Scalable Refinement Checking for Contract-Based Design - 06.6_1

Sankaranarayanan, Aviinaash

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability - 07.3_4

Sapatnekar, Sachin S.

Improving STT-MRAM Density through Multibit Error Correction - 07.5_3

Saraf, Naman

IIR Filters Using Stochastic Arithmetic - 04.4_1

Sarma, Santanu

Minimal Sparse Observability of Complex Networks: Application to MPSoC Sensor Placement and Run-time Thermal Estimation & Tracking - 11.6_1

Sassolas, Tanguy

Early Design Stage Thermal Evaluation and Mitigation: The Locomotiv Architectural Case - 11.3_4

Sassone, A.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors - 09.4_2

Sauer, Matthias

Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1

Sauer, Matthias

An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3

Sauer, Matthias

Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1

Saxena, Sharad

Efficient Performance Estimation with Very Small Sample Size via Physical Subspace Projection and Maximum A Posteriori Estimation - 08.7_1

Schacht, Andreas

Monitoring and WCET Analysis in COTS Multi-core-SoC-based Mixed-Criticality Systems - 04.2_3

Schaumont, Patrick

Analyzing and Eliminating the Causes of Fault Sensitivity Analysis - 08.3_2

Scheibler, Karsten

Efficient SMT-based ATPG for Interconnect Open Defects - 05.7_1

Schiffelers, R.R.H.

Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2

Schilders, Wil. H.A.

Implicit Index-aware Model Order Reduction for RLC/RC Networks 03.4_3

Schirner, Gunar

Automatic Specification Granularity Tuning for Design Space Exploration - 08.5_2

Schirrmeister, Frank

Future SoC Verification Methodology: UVM Evolution or Revolution? - 12.8

Schlichtmann, Ulf

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5

Schlichtmann, Ulf

Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test - 09.5

Schlichtmann, Ulf

Special Session: How Secure are PUFs Really? On the Reach and Limits of Recent PUF Attacks - 12.2_1

Schmaltz, Julien

Scalable Liveness Verification for Communication Fabrics - 05.5_1

Schmid, H.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Schmidt, V.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Schneider, Klaus

Isochronous Networks by Construction - 06.6_2

Schneider, Josef

Hardware-Based Fast Exploration of Cache Hierarchies in Application Specific MPSoCs - 10.4_2

Scholl, Stefan

Hardware Implementation of a Reed-Solomon Soft Decoder Based on Information Set Decoding - 08.4_3

Scholl, Christoph

Simple Interpolants for Linear Arithmetic - 05.5_3

Schubert, Tobias

Using MaxBMC for Pareto-Optimal Circuit Initialization - 06.5_1

Schüffny, R.

Integrated Circuits Processing Chemical Information: Prospects and Challenges - 12.1_1

Schulte, Michael

Process Variation-Aware Workload Partitioning Algorithms for GPUs Supporting Spatial-Multitasking - 07.4_4

Schumacher, Christoph

Time-Decoupled Parallel SystemC Simulation - 07.6_6

Schwarzer, Tobias

Model-Based Actor Multiplexing with Application to Complex Communication Protocols 08.5_4

Sedighi, Behnam

Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2

Sedighi, Behnam

Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study - 06.2_3

Seidl, Martina

Partial Witnesses from Preprocessed Quantified Boolean Formulas - 06.5_2

Seifert, Jean-Pierre

Physical Vulnerabilities of Physically Unclonable Functions - 12.2_5

Seitanidis, I.

ElastiStore: An Elastic Buffer Architecture for Network-on-Chip Routers - 09.2_3

Seitanidis, I.

Hardware Primitives for the Synthesis of Multithreaded Elastic Systems - 10.7_8

Sen, Shreyas

Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2

Seo, Woong

Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1

Seyler, Jan R.

A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3

Seyyedi, Razi

Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales - 02.7_1

Shafik, Rishad A.

A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6

Shafique, Muhammad

dSVM: Energy-Efficient Distributed Scratchpad Video Memory Architecture for the Next-Generation High Efficiency Video Coding - 02.5_2

Shafique, Muhammad

Compiler-Driven Dynamic Reliability Management for On-Chip Systems under Variabilities - 05.3_7

Shafique, Muhammad

Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing - 08.6_1

Shafique, Muhammad

hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6

Shafique, Muhammad

mDTM: Multi-Objective Dynamic Thermal Management for On-Chip Systems - 11.6_2

Shahrour, Anas

Unified, Ultra Compact, Quadratic Power Proxies for Multi-Core Processors - 11.6_6

Shan, ShuChang

Partial-SET: Write Speedup of PCM Main Memory - 03.5_5

Shang, Delong

Asynchronous Design for New On-Chip Wide Dynamic Range Power Electronics - 06.3_1

Shankar, Arunprasath

Cross-correlation of Specification and RTL for Soft IP Analysis - 10.5_4

Sharad, Mrigank

Brain-Inspired Computing with Spin Torque Devices - 08.8_2

Sharma, Namita

Energy Optimization in Android Applications through Wakelock Placement - 04.6_5

Sharma, Namita

Energy Efficient Data Flow Transformation for Givens Rotation Based QR Decomposition - 08.4_5

Shen, Hao

Battery Aware Stochastic QoS Boosting in Mobile Computing Devices - 07.3_5

Shen, Hao

Contention Aware Frequency Scaling on CMPs with Guaranteed Quality of Service - 10.3_3

Shi, Yiyu

Yield and Timing Constrained Spare TSV Assignment for Three-Dimensional Integrated Circuits - 05.3_6

Shi, Yiyu

Memcomputing: The Cape of Good Hope - 09.8_1

Shi, Yiyu

MSim: A General Cycle Accurate Simulation Platform for Memcomputing Studies - 09.8_2

Shi, Weidong

Programmable Decoder and Shadow Threads: Tolerate Remote Code Injection Exploits with Diversified Redundancy - 03.5_3

Shi, Weidong

Multi Resolution Touch Panel with Built-in Fingerprint Sensing Support - 09.3_3

Shin, Donghwa

Thermal Management of Batteries Using a Hybrid Supercapacitor Architecture - 11.6_3

Shin, Donghwa

FEPMA: Fine-Grained Event-Driven Power Meter for Android Smartphones Based on Device Driver Layer Event Monitoring - 12.6_4

Shrotri, Ulka

EDT: A Specification Notation for Reactive Systems - 08.5_3

Shu, Jiwu

p-OFTL: An Object-based Semantic-aware Parallel Flash Translation Layer - 06.6_4

Siddique, Umair

Towards the Formal Analysis of Microresonators Based Photonic Systems - 06.5_4

Sigl, Georg

Increasing the Efficiency of Syndrome Coding for PUFs with Helper Data Compression - 04.3_3

Signorello, G.

III-V Semiconductor Nanowires for Future Devices - 09.1_1

Silvano, Cristina

Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon - 08.2_2

Silvano, Cristina

DeSpErate: Speeding-up Design Space Exploration by Using Predictive Simulation Scheduling - 08.5_6

Silveira, L. Miguel

Efficient Analysis of Variability Impact on Interconnect Lines and Resistor Networks - 03.4_2

Simunic Rosing, Tajana

A Linux-Governor Based Dynamic Realiability Manager for Android Mobile Devices - 05.3_5

Sinanoglu, Ozgur

Approximating the Age of RF/Analog Circuits through Re-characterization and Statistical Estimation - 02.7_6

Singh, Bhanu

Cross-correlation of Specification and RTL for Soft IP Analysis - 10.5_4

Själander, Magnus

Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD³) - 04.5_6

Slamani, Mustapha

Built-In Self-Test and Characterization of Polar Transmitter Parameters in the Loop-Back Mode - 12.7_2

Smailbegovic, Fethulah

Hacking and Protecting IC Hardware - 05.2

Smith, Aaron

EVX: Vector Execution on Low Power EDGE Cores - 02.5_4

Sohn, M.-P.

Application of Mission Profiles to Enable Cross-Domain Constraint-Driven Design - 03.8_4

Sohrmann, Christoph

Probabilistic Standard Cell Modeling Considering Non-Gaussian Parameters and Correlations - 08.7_5

Sokhin, Vitali

Effective Post-Silicon Failure Localization Using Dynamic Program Slicing - 11.4_3

Sokolov, Danil

Design of Safety Critical Systems by Refinement - 04.6_4

Son, Sang H.

A Layered Approach for Testing Timing in the Model-Based Implementation - 07.6_4

Song, Seokwoo

Energy-Efficient Scheduling for Memory-Intensive GPGPU Workloads - 02.5_1

Song, Yang

Zonotope-based Nonlinear Model Order Reduction for Fast Performance Bound Analysis of Analog Circuits with Multiple-interval-valued Parameter Variations - 02.4_2

Sonza Reorda, M.

GPGPUs: How to Combine High Computational Power with High Reliability - 11.8

Sonza Reorda, Matteo

An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults - 05.7_3

Sorin, Daniel J.

Nostradamus: Low-Cost Hardware-Only Error Detection for Processor Cores - 06.7_1

Sölter, Jan

PUF Modeling Attacks: An Introduction and Overview - 12.2_3

Soudbakhsh, Damoon

Fault-tolerant Control Synthesis and Verification of Distributed Embedded Systems - 03.6_3

Sousa, R.

Magnetic Memories: From DRAM Replacement to Ultra Low Power Logic Chips - 10.1_3

Spägele, Matthias

A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3

Spasic, Jelena

Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3

Sridhar, Arvind

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs - 06.1_2

Stamelakos, Ioannis

Voltage Island Management in Near Threshold Manycore Architectures to Mitigate Dark Silicon - 08.2_2

Stefanni, Francesco

Moving from Co-Simulation to Simulation for Effective Smart Systems Design - 10.4_5

Stefanov, Todor

Resource Optimization for CSDF-modeled Streaming Applications with Latency Constraints - 07.6_3

Stefanov, Todor

System-level Scheduling of Real-time Streaming Applications Using a Semi-partitioned Approach - 12.5_4

Steinhorst, Sebastian

Optimal Dimensioning of Active Cell Balancing Architectures - 06.3_3

Steininger, Andreas

A Tree Arbiter Cell for High Speed Resource Sharing in Asynchronous Environments - 10.7_2

Stenström, Per

Effective Resource Management towards Efficient Computinga - 06.1_3

Stoimenov, Nikolay

Mapping Mixed-Criticality Applications on Multi-Core Architectures - 05.1_3

Streichert, Thilo

A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support - 02.3_3

Stroobandt, Dirk

Improving Hamiltonian-based Routing Methods for On-chip Networks: A Turn Model Approach - 09.2_5

Stroobandt, Dirk

Automating Data Reuse in High-Level Synthesis - 10.7_5

Stuijk, S.

Timing Analysis of First-Come First-Served Scheduled Interval-Timed Directed Acyclic Graphs - 10.5_2

Stuijk, Sander

Memory-Constrained Static Rate-Optimal Scheduling of Synchronous Dataflow Graphs via Retiming - 11.5_3

Stuijt, Jan

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing - 08.2_3

Su, Yongtao

System-level Design Methodology Enabling Fast Development of Baseband MP-SoC for 4G Small Cell Base Station - 08.1_2

Suárez, Darío

Dynamic Construction of Circuits for Reactive Traffic in Homogeneous CMPs - 09.2_4

Subramanyan, Pramod

Formal Verification of Taint-propagation Security Properties in a Commercial SoC Design - 11.3_3

Sudowe, Patrick

A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications - 12.3_2

Sullivan, Dean

Real-Time Trust Evaluation in Integrated Circuits - 04.7_1

Sun, Haiyan

Lifetime Holes Aware Register Allocation for Clustered VLIW Processors - 04.6_7

Sun, Luo

A Low Power and Robust Carbon Nanotube 6T SRAM Design with Metallic Tolerance - 05.4_6

Susin, Altamiro

hevcDTM: Application-Driven Dynamic Thermal Management for High Efficiency Video Coding - 08.6_6

Swaminathan, Karthik

Modeling Steep Slope Devices: From Circuits to Architectures - 06.2_2

Syed, Rizwan

Thermal-Aware Frequency Scaling for Adaptive Workloads on Heterogeneous MPSoCs - 10.6_1

Sylvester, Dennis

Energy Efficient In-Memory AES Encryption Based on Nonvolatile Domain-wall Nanowire - 07.5_4