W10 TRUDEVICE 2015: Workshop on Trustworthy Manufacturing and Utilization of Secure Devices

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Date: 
2015-03-13
Time: 
08:30-17:00
Location / Room: 
Les Bans

General Chair

Giorgio Di Natale, LIRMM, FR (Contact Giorgio Di Natale)

General Vice-Chair

Ilia Polian, University of Passau, DE (Contact Ilia Polian)

Programme Committee Chair

Bossuet Lilian, University of St. Etienne, FR (Contact Bossuet Lilian)

Programme Committee Vice-Chair

Nicolas Sklavos, Technological Educational Institute of Patras, GR (Contact Nicolas Sklavos)

Scope of the workshop and target audience

Hardware security is becoming increasingly important for many embedded systems ranging from small RFID tag to satellites orbiting the earth. While secure applications such as public services, communication, control or healthcare keep growing, hardware devices that implement these applications become the Achille's heel of such systems.

The TRUDEVICE Workshop will provide an environment for researchers from academic and industrial domains who want to discuss recent findings, theories and on-going work on all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization. Program will include invited talks, contributed talks and work in progress. Topics of the workshop include but are not limited to:

  • Manufacturing test of secure devices
  • Trustworthy manufacturing of secure devices
  • PUFs and TRNGs
  • Hardware Trojans in IPs and ICs
  • Reconfigurable devices for secure functions
  • Fault attack injection, detection and protection
  • Validation, Evaluation

The workshop will be organized in the framework of the COST Action IC1204 (TRUDEVICE). So far, we organized 2 workshops in the same context, the first in Avignon in conjunction with ETS'13 on May 30, 2013; the second as stand-alone event in Freiburg on December 12-13, 2013.

Event format

This workshop would give a large place to Ph.D student presentations and preliminary works. The last TRUDEVICE workshop in conjunction with ETS proposed two types of contribution, short and long. We think that this organization is well dedicated to this workshop. A call for short papers (2 pages, SP) and long paper (from 4 pages to 6 pages, LP) will be distributed, mainly by using the TRUDEVICE mailing list but also larger to try to attracts people beyond the cost action. The short papers will be presented in 15 min and the long papers will be presented in 20 min. Before the morning session and the afternoon session, two keynotes will be presented by the following speakers:

  • Pr. Jean-Luc Danger, Telecom ParisTech, France - Topic: The pros and cons of technological dispersion for security: PUF, TRNG and side-channel countermeasures
  • Pr. Tim Güneysu, Ruhr University Bochum, Germany - Topic: Secure reconfigurable Hardware

Two poster sessions (during the two coffee breaks) will be dedicated to the presentation of collaborative projects which involve members of the cost action TRUDEVICE. A call for poster will be distributed. Submission to the poster session will consist in fill out a form with the following information: project title/acronym, a very-short presentation of the project objectives, list of partners, funding source and duration).

Agenda

TimeLabelSession
08:30W10.1Opening Session
08:30W10.1.1TRUDEVICE: Trustworthy Manufacturing and Utilization of Secure Devices
Giorgio Di Natale1, Ilia Polian2, Bossuet Lilian3 and Nicolas Sklavos4
1LIRMM, FR; 2University of Passau, DE; 3University of St. Etienne, FR; 4KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR

08:45W10.2Keynote Talk 1

Chair:
Giorgio Di Natale, LIRMM, FR, Contact Giorgio Di Natale

08:45W10.2.1The pros and cons of technological dispersion for security: PUF, TRNG and side-channel countermeasures
Jean-Luc Danger, Télécom ParisTech, FR

09:30W10.3Session 1

Chair:
Bossuet Lilian, University of St. Etienne, FR, Contact Bossuet Lilian

09:30W10.3.1Analysis and utilization of deviations in RO-PUFs under altered FPGA designs
Linus Feiten, Tobias Martin and Bernd Becker, University of Freiburg, DE

09:45W10.3.2Ring Oscillators Analysis for FPGA Security Purposes
Mario Barbareschi1, Lionel TORRES2 and Giorgio Di Natale3
1University of Naples Federico II, IT; 2LIRMM - University Montpellier 2, FR; 3LIRMM, FR

10:00W10.3.3Enhanced TERO-PUF design and characterization with FPGA
Cedric Marchand, Abdelkarim Cherkaoui and Bossuet Lilian, University of St. Etienne, FR

10:15W10.3.4Implementing Reliable Mechanisms for IP Protection on Low-End FPGA devices
Mario Barbareschi, Antonio Mazzea and Pierpaolo Bagnasco, University of Naples Federico II, IT

10:30W10.4Poster Session 1

Chair:
Ilia Polian, University of Passau, DE, Contact Ilia Polian

10:30W10.4.1Functional Locking Modules for Design Protection of Intellectual Property Cores
Brice Colombier and Bossuet Lilian, University of St. Etienne, FR

10:30W10.4.23D-NoC protection capabilities and threats: The TSV risk
Martha Johanna Sepulveda1, Guy Gogniat2 and Marius Strum1
1University of São Paulo, BR; 2Universite de Bretagne-Sud / Lab-STICC, FR

10:30W10.4.3Hardware Trojans in TRNGs
Honorio Martin1, Pedro Paris-Lopez1, Enrique San Millan1, Juan E. Tapidor1 and Nicolas Sklavos2
1University Carlos III of Madrid, ES; 2KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR

10:30W10.4.4Development of a Layout-Level Hardware Obfuscation Tool
Shweta Malik1, Georg T. Becker2, Christof Paar2 and Wayne P. Burleson1
1University of Massachusetts, US; 2Horst Görtz Institute for IT-Security, Ruhr-University Bochum, DE

10:30W10.4.5GET - Program for the Generation and Analysis on Nonlinear Elements
Stjepan Picek1 and Lejla Batina2
1Faculty of Electrical Engineering and Computing, HR; 2Radboud University Nijmegen, NL

10:30W10.4.6Why you should care about leading-edge Software Engineering?
Tiziana Margaria, University of Limerick (Ireland) and Lero - The Irish Software Research Center, IE

10:30W10.4.7Error detection and correction for lightweight cryptographic algorithms
Francesco Regazzoni1, Andrey Bogdanov2, Luca Breveglieri3 and Israel Koren4
1Université catholique de Louvain and ALaRI, CH; 2Technical University of Denmark, DK; 3Polimi, IT; 4University of Massachusetts, US

10:30W10.4.8Fine grain partial reconfiguration for fault emulation and precise LUT modification
L.A. Cardona1, Bibiana Lorente2 and C. Ferrer3
1IEEC-UAB, ES; 2CNM-CSIC, ES; 3EEC-UAB, ES

11:30W10.5Session 2

Chair:
Nicolas Sklavos, KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR, Contact Nicolas Sklavos

11:30W10.5.1Hierarchical Secure DfT
Mafalda Cortez1, Said Hamdioui2, Giorgio Di Natale3, Marie-Lise Flottes3 and Bruno Rouzeyre3
1TU Delft, NL; 2Delft University of Technology, NL; 3LIRMM, FR

12:00W10.5.2Integrated Sensors: A Backdoor for Hardware Trojan Activation
Xuan-Thuy Ngo, Zakaria Najm, Shivam Bhasin, Sylvain Guilley and Jean-Luc Danger, Télécom ParisTech, FR

13:00W10.6Keynote Talk 2

Chair:
Ilia Polian, University of Passau, DE, Contact Ilia Polian

13:00W10.6.1Protecting Cryptographic Implementations on Reconfigurable Devices
Tim Güneysu, Ruhr University Bochum, DE

13:45W10.7Session 3

Chair:
Bossuet Lilian, University of St. Etienne, FR, Contact Bossuet Lilian

13:45W10.7.1Towards Generic Countermeasures Against Fault Injection Attacks
Pablo Rauzy and Sylvian Guilley, Télécom ParisTech, FR

14:00W10.7.2Analysis of laser-induced errors: RTL fault model versus layout locality characteristics
Athanasios Papadimitriou1, David Hely2, Vincent Beroulle2, Paolo Maistri3 and Regis Leveugle3
1Univ. Grenoble Alpes, LCIS Laboratory, FR; 2Univ. Grenoble Alpes, FR; 3TIMA Laboratory, FR

14:15W10.7.3Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology
Stephan De Castro and Giorgio Di Natale, LIRMM, FR

14:30W10.7.4Dynamic Fault Model for Long Duration Laser-Induced Fault Simulation
Feng Lu, Giorgio Di Natale, Marie-Lise Flottes and Bruno Rouzeyre, LIRMM, FR

14:30W10.8Poster Session 2

Chair:
Nicolas Sklavos, KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR, Contact Nicolas Sklavos

14:30W10.8.1The Influence of Real-Time Scheduling on Differential Power Analysis Attacks
Ke Jiang1, Lejla Batina2, Petru Eles1 and Zebo Peng1
1Linköping University, SE; 2Radboud University Nijmegen, NL

14:30W10.8.2Exploring RNS in the design of improved RSA implementations
Juvenal Araujo, Pedro Matutino, Leonel Sousa and Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT

14:30W10.8.3CAESAR and NORX - Developing the Future of Authenticated Encryption
Jean-Philippe Aumasson1, Philipp Jovanovic2 and Samuel Neves3
1Kudelski Security, CH; 2University of Passau, DE; 3University of Coimbra, GR

14:30W10.8.4Power and Electromagnetic Analysis for Online Template Attacks
Margaux Dugardin1, Louiza Papachristodoulou2, Zakaria Najm1, Lejla Batina3, Jean-Luc Danger1, Sylvain Guilley1, Jean-Christophe Courrege4, Anne-Sophie Rivemale4 and Carine Therond4
1Télécom ParisTech, FR; 2Radboud University Nijmegen,, NL; 3Radboud University Nijmegen, NL; 4Thales Communications & Security, FR

14:30W10.8.5Search Strategy for Fault Injection using Memetic Algorithms
Stjepan Picek1, Pieter Buzing2 and Lejla Batina3
1Faculty of Electrical Engineering and Computing, HR; 2Riscure BV, NL; 3Radboud University Nijmegen, NL

14:30W10.8.6Insights into the Correlation between the Processed Data and its Power Traces
Miryam Haber, Binyamin Frankel, Moshe Avital, Itamar Levi, Osnat Keren and Alexander Fish, Bar-Ilan University, IL

14:30W10.8.7Tuning of randomized windows against simple power analysis for scalar multiplication on elliptic curves
Simon Pontie1, Paolo Maistri2 and Regis Leveugle2
1University Grenoble Alpes, FR; 2TIMA Laboratory, FR

15:00W10.9Session 4

Chair:
Giorgio Di Natale, LIRMM, FR, Contact Giorgio Di Natale

15:00W10.9.1Public Key cryptographic primitive design and protection against fault and power analysis attacks
Apostolos P. Fournaris and Nicolas Sklavos, KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR

15:15W10.9.2On the Use of Error Detecting and Correcting Codes to Boost Security in Caches against Side Channel Attacks.
Madalin Neagu1, Salvador Manich2 and Liniu Miclea1
1Technical University of Cluj-Napoca, RO; 2Universitat Politecnica de Catalunya, ES

15:30W10.9.3A Side-Channel Attack Against Secret Permutation on an Embedded McEliece Cryptosystem
Tania Richmond1, Martin Petrvalsky2 and Milos Drutarovsky2
1Univ. St. Etienne, FR; 2Technical University of Kosic, SK

15:45W10.10Session 5

Chair:
Nicolas Sklavos, KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR, Contact Nicolas Sklavos

15:45W10.10.1Investigating TERO for Hardware Trojan Horse Detection
Paris Kitsos1 and Artemios G. Voyiatzis2
1Technological Educational Institute of Western Greece, GR; 2ISI, GR

16:00W10.10.2Insertion and evaluation of Hardware Trojans in Processors
Ioannis Voyiatzis, Costas Efstathiou and Thanos Milidonis, Technological Educational Institute of Athens, GR

16:15W10.10.3Security of ICs from Hardware Trojans
Georgina Kalogeridou1, Andrew W. Moore1, Nicolas Sklavos2 and Odysseas Koufopavlou3
1Computer Laboratory, University of Cambridge, GB; 2KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR; 3University of Patras, GR

16:30W10.10.4HINT: Holistic Approaches for Integrity of ICT-Systems
Ingrid Verbauwhede and Dave Singelee, KU Leuven and UCLA, BE

16:45W10.11Closing Session
16:45W10.11.1Conclusions & Outlook: Round Table
Giorgio Di Natale1, Ilia Polian2, Bossuet Lilian3 and Nicolas Sklavos4
1LIRMM, FR; 2University of Passau, DE; 3University of St. Etienne, FR; 4KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR