M06 Testing of TSV-Based 2.5D- and 3D-Stacked ICs

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Agenda

Agenda

TimeLabelSession
09:30M06.1Session 1
00:00M06.1.1Introduction

00:00M06.1.2Overview of 2.5D- and 3D-technology

00:00M06.1.33D test flows and test contents

00:00M06.1.43D test access: wafer probing (industry/research)

11:30M06.2Session 2
00:00M06.2.13D test access: DfT architecture (incl. IEEE P1838) and optimizations

00:00M06.2.23D cost flow modeling (with case studies)

00:00M06.2.3Conclusion

Groups: