Test pattern generation (TPG); fault simulation; high-level TPG; delay TPG; low-power TPG; TPG for memories and FPGAs; system test; diagnosis; debug; post-silicon validation; testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, System-on-Package, Package on Package, board, system; testing 3D chips; Network-on-Chip test; hardware/software system test; processor based test; infrastructure IP.
Chair: Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact
Co-Chair: Bernd Becker, University of Freiburg, DE, Contact
Members: