Technical Programme Committee 2014

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Topic: T2 Test Generation, Simulation, Diagnosis and System Test

Test pattern generation (TPG); fault simulation; high-level TPG; delay TPG; low-power TPG; TPG for memories and FPGAs; system test; diagnosis; debug; post-silicon validation; testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, System-on-Package, Package on Package, board, system; testing 3D chips; Network-on-Chip test; hardware/software system test; processor based test; infrastructure IP.

Chair: Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact

Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

Members:

  • Piet Engelke, Infineon, DE, Contact
  • Nicola Nicolici, McMaster University, CA, Contact
  • matteo sonza reorda, politecnico di torino - DAUIN, IT, Contact
  • Arnau Virazel, LIRMM / Univ. Montpellier, FR, Contact
  • Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact