Topic: D8 Network on Chip

Architecture, modeling and design techniques for Networks-on-Chips; design methods and architectures for the on-chip interconnection network: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security, power management and fault tolerance; techniques and methodologies for NoC testing; GALS synchronization architectures for NoCs; physical design techniques and methodologies; integration of external interfaces/memory controllers with NoCs; cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; programming models for NoC-based platforms; industrial applications of NoCs; design of NoCs based on alternative technologies such as photonics/optics, wireless, 3D stacking.

Chair: Federico Angiolini, iNoCs, CH, Contact

Co-Chair: Fabien Clermidy, CEA-LETI, FR, Contact

Members:

• Paul Ampadu, University of Rochester, US, Contact
• John Bainbridge, Sonics, US, Contact
• Davide Bertozzi, University of Ferrara, IT, Contact
• Luca Carloni, Columbia University, US, Contact
• Koushik Chakraborty, Utah State University, US, Contact
• Masoud Daneshtalab, UTU, FI, Contact
• Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
• Josè Flich, Universidad Politecnica de Valencia, ES, Contact
• Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
• Andreas Hansson, ARM Ltd, GB, Contact
• Shaahin Hessabi, Sharif University of Technology, IR, Contact
• Jung Ho Ahn, Seoul National University, KR, Contact
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• Hiroki Matsutani, Keio University, JP, Contact
• Steven Nowick, Columbia University, US, Contact
• Pascal VIVET, CEA-LETI, FR, Contact
• Sungjoo Yoo, POSTECH, KR, Contact