Topic: D5 Power Estimation and Optimization

Algorithms, techniques and tools for power and temperature modeling, estimation and optimization of electronic systems applicable at all levels of the design hierarchy, from system-level specification to layout, including software and run-time management.

Chair: Jian-Jia Chen, KIT, DE, Contact

Co-Chair: William Fornaciari, Politecnico di Milano, IT, Contact

Members:

• Yiran Chen, Seagate Technology, US, Contact
• Josef Haid, Infineon, AT, Contact
• Joerg Henkel, Karlsruhe Institute of Technology, DE, Contact
• Francesc Moll, Universitat Politècnica de Catalunya, ES, Contact
• Wolfgang Nebel, Oldenburg University and OFFIS, DE, Contact
• Mauro Olivieri, Sapienza University of Rome, IT, Contact
• Massimo Poncino, Politecnico di Torino, IT, Contact
• Anand Raghunathan, Purdue University, US, Contact
• Olivier Sentieys, CAIRN,IRISA, FR, Contact
• Xiaorui Wang, University of Ohio, US, Contact
• Chia-Lin Yang, National Taiwan University, TW, Contact