Topic: D15 Parasitic Extraction, Modeling and Optimization of Interconnect, TSV and Power Grids

Electrical and thermal characterization, modeling and optimization of on and off chip interconnects, Through Silicon Vias (TSV), 3D interconnects, interposer, and packaging; wireless interconnects via capacitive/inductive coupling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate; EMC issues in interconnects: electromagnetic emission, susceptibility and compatibility; chip-package co-design; high-speed channel and equalizer modeling, design, and measurement; macro-modeling, behavioral, and reduced order modeling.

Chair: Stefano Grivet-Talocia, Politecnico di Torino, IT, Contact

Co-Chair: Luca Daniel, Massachusetts Institute of Technology, US, Contact

Members:

• Dipanjan Gope, Indian Institute of Science, IN, Contact
• L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact
• Dries Vande Ginste, University of Ghent, BE, Contact