Topic: D13 Physical Synthesis and Verification

Floorplanning; automatic place and route; module generation; design rule checking; layout characterization; verification; deep sub-micron, high-speed design; interconnect-driven and performance-driven layout: process technology developments; design for manufacturability

Chair: Ralph Otten, TU Eindhoven, NL, Contact

Co-Chair: Patrick Groeneveld, Synopsys, US, Contact

Members:

• Azadeh Davoodi, University of Wisconsin - Madison, US, Contact
• Jens Lienig, Technical University of Dresden, DE, Contact
• Sven Peyer, IBM, DE, Contact
• Jose Pineda de Gyvez, NXP Semiconductors, NL, Contact
• Carl Sechen, UT Dallas, US, Contact