Topic: D12 Logic Synthesis and Timing Analysis

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design, statistical timing analysis, timing closure; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; PLD and FPGA synthesis; arithmetic circuits.

Chair: José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact

Co-Chair: Valentina Ciriani, University of Milano, IT, Contact

Members:

• Michel Berkelaar, Delft University of Technology, NL, Contact
• Jordi Cortadella, Universitat Politecnica de Catalunya, ES, Contact
• Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
• John Hayes, University of Michigan, US, Contact
• Sanjay Kumar, Synopsys, US, Contact
• Davide Pandini, STMicroelectronics, IT, Contact
• Tiziano Villa, University of Verona, IT, Contact
• Vladimir Zolotov, IBM T.J. Watson Research Center, US, Contact