W7 Memristor Science & Technology
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 08:30 | W7.1 | Opening Session Chair: Co-Chair: |
| 08:45 | W7.2 | Invited Talk by Prof. L. O. Chua |
| 08:45 | W7.2.1 | Memristor: State-of-the-Art L. O. Chua, University of California, Berkeley, US This exposition shows that the potassium ion-channels and the sodium ion-channels that are distributed over the entire length of the axons of our neurons are in fact locally-active memristors. In particular, they exhibit all of the fingerprints of memristors, including the characteristic pinched hysteresis Lissajous figures in the voltage-current plane, whose loop areas shrink as the frequency of the periodic excitation signal increases. Moreover the pinched hysteresis loops for the potassium ion-channel memristor, and the sodium ion-channel memristor, from the Hodgkin-Huxley axon circuit model are unique for each periodic excitation signal. An in-depth circuit-theoretic analysis and characterizations of these two classic biological memristors are presented via their small-signal memristive equivalent circuits, their frequency response, and their Nyquist plots. Just as the Hodgkin-Huxley circuit model has stood the test of time, its constituent potassium ion-channel and sodium ion-channel |
| 10:00 | W7 | Coffee Break |
| 10:15 | W7.4 | Session 1 |
| 10:15 | W7.4.1 | Invited Talk: Resistive Switching - From Basic Switching Mechanism to Device Applications Thomas Mikolajick1, Hannes Mähne2, H. Wylezich2 and Stefan Slesazeck2 1NaMLab gGmbH and Technische Universität Dresden, DE; 2NaMLab gGmbH, DE Resistive switching mechanisms are under intense study in the last 15 years mainly for applications in next generation memories. A variety of physical mechanisms exist that lead to different switching characteristics. Based on the portfolio of different device characteristics the device properties may be adjusted to different application needs. In this talk the progress in tailoring resistive switching characteristics both from literature as well as from the authors group will be shown and conclusions for prospects in semiconductor memories and other applications will be drawn. |
| 11:15 | W7.4.2 | The art of SPICE modeling of memristive systems Dalibor Biolek, University of Defense and Brno University of Technology, CZ A methodology for accurate and reliable modeling of memristive devices in SPICE environment is presented. Due to specific features of SPICE-family programs, the simulation results can be burdened with errors, either evident or not apparent at first sight, or the solution may not be found at all. The above two kinds of problems, called imperfections and non-convergence issues, can be magnified in circuits containing memristive elements with a specific hysteresis behavior. Four key factors, influencing the accuracy and reliability, are discussed: numerical limits in SPICE, rules of building up behavioral models, the way of modeling the state and port equations, and setting the parameters of the analysis. The recommendations are applicable to a wide class of SPICE-family simulation programs. Demonstrations are given for PSpice and HSPICE. |
| 12:00 | W7 | Lunch |
| 13:00 | W7.5 | Session 2 |
| 13:00 | W7.5.1 | Modeling and simulation of memristive devices for memory and logic applications Stephan Menzel1 and Rainer Waser2 1Forschungszentrum Jülich, DE; 2RWTH Aachen Universität, DE Redox-based mesistive switching devices are a potential candidate for future non-volatile memory and logic applications. To enable circuit design using memristive devices predictive simulation models are required. In this work basic requirements are defined that needs to be fulfilled to accurately model memristive devices. In addition, a physics-based modeling approach for the resistive switching in ECM cells is presented which fulfills the relevant criteria. It is based on the electrochemical driven growth and dissolution of a metallic filament and covers self-consistently the basic experimental characteristics: I-V characteristics, nonlinear switching kinetics, and multilevel switching behavior. |
| 13:45 | W7.5.2 | Memory Intensive Computing Shahar Kvatinski, Technion – Israel Institute of Technology, IL Over the past years, new memory technologies such as RRAM, STT-MRAM, PCM etc., have emerged. These technologies, located in the metal layers of the chip, are relatively fast, dense, and power-efficient, and can be considered as memristors. Usually, the use of these devices has been limited to flash, DRAM, and SRAM replacement. This talk is focused on different uses of memristors. For example, new memory structures, different than the conventional memory hierarchy, opening opportunity to a new era in computer architecture - the era of Memory Intensive Computing. Memristors can also be integrated with CMOS in logic circuits. Alternatively, they can be used as a stand-alone logic, suitable to perform logic within the memory and provide opportunity for new computer architectures, different than classical von Neumann. |
| 14:30 | W7 | Coffee Break |
| 15:00 | W7.6 | Session 3 |
| 15:00 | W7.6.1 | Ferroelectric Memristors for Neuromorphic Computing Sören Boyn, CNRS/Thales, FR Thanks to the progress in Nanotechnologies and Material Science, physicists and condensed matter scientists have recently been able to build smart nano-devices with enhanced capabilities. Some of these new devices show functionalities that could be extremely interesting for bio-inspired computing. It has been demonstrated for example that some analog and tunable nano-resistors called Memristors can mimic synapses on silicon. The industry is already developing dense networks of these nano-devices for classical digital memories. It is therefore no longer a dream to envisage building bio-inspired chips based on large-scale, high density parallel networks of these advanced devices, and taking advantage of their full functionalities. What's more, the inherent qualities of massively parallel architectures: the speed, the tolerance to defects and the low power consumption are more and more appreciated these days when computer processors are heating so much that they cannot be used at all times, and when transistors are shrinking so much that they will no longer be reliable. It is becoming a common thesis that bio-inspired chips such as Artificial Neural Networks will soon enter the market as a back-up or accelerator of more traditional computing architectures. In this talk, after a brief introduction on memristors nano-devices and their applications, I will focus on our work: the development of a new generation of memristors, based on purely electronic effects, the ferroelectric memristors. I will show that, by tuning interface properties and finely engineering the dynamics of ferroelectric polarization, we can control the response of these memristors. Furthermore, I will demonstrate their suitability in terms of endurance and retention. |
| 15:00 | W7.6.2 | Is memristor the 4th circuit element? Frank Zhigang Wang, School of Computing University of Kent Canterbury, GB Chua proposed a Basic Circuit Element Quadrangle including the three classic elements (resistor, inductor and capacitor) and his formulated, named memristor as the fourth element. Based on an observation that this quadrangle may not be perfectly symmetric, we propose a Basic Circuit Element Triangle, in which memristor as well as mem-capacitor and mem-inductor lead three basic element classes, respectively. An intrinsic mathematical relationship is found to support this new classification. We believe that this triangle is concise, mathematically sound and aesthetically beautiful, compared with Chua's quadrangle. The importance of finding a correct circuit element table is similar to that of Mendeleev's Periodic Table of Chemical Elements in Chemistry. A correct circuit element table would also request to rewrite the physics textbooks. |
| 15:00 | W7.6.3 | NbOx/Nb2O5 memristor modeling based on Chua's Unfolding Principle Alon Ascoli1, Stefan Slesazeck2, Hannes Mähne2, Ronald Tetzlaff1 and Thomas Mikolajick3 1Technische Universität Dresden, DE; 2NaMLab gGmbH, DE; 3NaMLab gGmbH and Technische Universität Dresden, DE Prof. Chua has recently introduced a systematic approach to the modeling of memristors known as Unfolding Principle. Sharing Chua's opinion that the availability of a general mathematical framework capable to capture the dynamics of real memristors would boost the ongoing exploration of their full potential in various applications developing new types of circuits including non-volatile memories, neuromorphic systems, spike-based signal processing machines and sensor systems, in this presentation we introduce a Unfolding Principle-based model for the threshold switching behavior of a NbOx/Nb2O5 memristor fabricated at NaMLab. The accuracy of the proposed mathematical description is demonstrated through a number of case studies. The proposed model is accurate yet simple and thus suited for time-efficient circuit simulations. The availability of reliable mathematical frameworks, such as the one proposed here, would certainly pave the way towards a more rapid, extensive and intensive introduction of the memristor into the realm of circuit elements at disposal of integrated circuit designers. |
| 15:00 | W7.6.4 | Pattern Classification and Recognition with Memristive Circuits Fabien Alibart1 and D. B. Strukov2 1CNRS, FR; 2University of California at Santa Barbara, US We will discuss recent experimental results on pattern classification and recognition tasks implemented with memristive [1] (ReRAM [2]) neural networks. The Pt/TiO2-x/Pt memristive devices (Fig. 1a, b), which are utilized in both demonstrations, are fabricated with nanoscale e-beam-defined protrusion which localizes the active area during the forming process to ~(20 nm)3 volume and as a result helps in improving device yield. In particular, we will first discuss demonstration of pattern classification task for 3×3 binary images by a single-layer perceptron network implemented with 10 x 2 memristive crossbar circuits (Fig. 1c) in which synaptic weights are realized with memristive devices. The perceptron circuit is trained by ex-situ and in-situ methods to perform binary classification for a set of patterns from an original work by Widrow [3]. In the ex-situ case, the synaptic weights are calculated on the precursor software-based network and then imported sequentially to the crossbar circuits using variation-tolerant programming algorithm [4]. For the in-situ training, the weights are adjusted in parallel following perceptron learning rule by applying voltage pulses from pre-synaptic and post-synaptic neurons. Both approaches work successfully (Fig. 1d) despite significant variations in switching behavior of memristive devices as well as half-select and leakage problems in crossbar circuits [5]. |
| 15:00 | W7.6.5 | Memristor crossbar array circuits for neuromorphic applications Kyeong-Sik Min, Kookmin University, KR Crossbar array architecture is the most suitable to realize high-density memristor-based synapses. In this presentation, we discuss various crossbar array circuits for mimicking synaptic functions in terms of area, power, etc. In addition, variations in fabrication process, power supply voltage, etc that can affect the synaptic functions of memristor-based crossbar array will be analyzed and discussed in this presentation. |
| 16:40 | W7.7 | Closing Session |
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