M11 Post-Silicon Validation and Debug: Best Practices and Disruptive Innovation

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Konferenz 6


Nagib Hakim, Intel Corporation Santa Clara, US
Subhasish Mitra, Stanford University, US
Amir Nahir, IBM Research Labs Haifa, IL
Alan Hu, University of British Columbia, CA


Hardware failures are a growing concern as electronic systems become more complex, interconnected, and pervasive. The complexity challenge is further exacerbated by new ways of improving energy efficiency of electronic systems with the slowdown of CMOS (Dennard) scaling: increasing amounts of cores, uncore components, and accelerators; increasing degrees of adaptivity; and, increasing levels of heterogeneous integration. All these features and their complex interactions make future systems highly vulnerable to design flaws (bugs) that can jeopardize correct system operation and/or introduce security vulnerabilities. Existing validation methods barely cope with today's complexity. Traditional pre-silicon verification alone is no longer adequate. Post-silicon validation involves operating manufactured ICs in actual application environments to detect and fix bugs. Existing post-silicon practices are ad-hoc, and their costs are rising faster than design cost. Effective post-silicon validation requires a radical departure from today's ad-hoc practices to structured techniques. A wide range of topics will be covered in this tutorial, from best practices at leading companies to recent research results that are immediately applicable. Examples include: 1. overview of validation product life cycle; 2. trade-offs in pre- vs. post-silicon validation; 3. validation test content generation using the concept of exercisers; 4. validation infrastructure including triggers, observability structures, and performance monitors; 5. structured and systematic techniques such as QED (Quick Error Detection); 6. coverage metrics; 7. logic and electrical bug validation and debug techniques; 8. formal techniques for post-silicon validation and debug; 9. post-silicon repair, survivability, and resiliency; 10. bug benchmarks and industrial case studies.



14:30M11.1Session 1
00:00M11.1.1Big Picture (Nagib Hakim, Subhasish Mitra, Amir Nahir)
Nagib Hakim1, Subhasish Mitra2 and Amir Nahir3
1Intel Corporation Santa Clara, US; 2Stanford University, US; 3IBM Research Labs Haifa, IL

16:30M11.2Session 2
00:00M11.2.1Observability enhancement during post-silicon validation (Alan Hu, Subhasish Mitra)
Alan Hu1 and Subhasish Mitra2
1University of British Columbia, CA; 2Stanford University, US