M06 Testing of TSV-Based 2.5D- and 3D-Stacked ICs

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Location / Room: 
Konferenz 5


Erik Jan Marinissen, IMEC - Leuven, BE
Krishnendu Chakrabarty, Duke University - Durham, NC, US

Target Audience: Test and design-for-test engineers and their managers; test methodology developers; test-automation tool developers; researchers, university professors, and students.  


Stacked ICs with vertical interconnect containing fine-pitch micro-bumps and through-silicon vias (TSVs) are a hot-topic in design and manufacturing communities. These 2.5D- and 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, testing for manufacturing defects remains an obstacle and potential showstopper before stacked-die products can become a reality. There are concerns about the cost or, even worse, feasibility of testing such TSV-based 3D chips. In this tutorial, we present key concepts in 3D technology, terminology, and benefits. We discuss design and test challenges and emerging solutions for 2.5D- and 3D-SICs. Topics to be covered include an overview of 3D integration and trendsetting products such as a 2.5D-FPGA and 3D-stacked memory chips, test flows and test content for 3D chips, advances in wafer probing, 3D design-for-test architectures and ongoing IEEE P1838 standardization efforts for test access, and 3D test cost modeling and test-flow selection.



09:30M06.1Session 1

00:00M06.1.2Overview of 2.5D- and 3D-technology

00:00M06.1.33D test flows and test contents

00:00M06.1.43D test access: wafer probing (industry/research)

11:30M06.2Session 2
00:00M06.2.13D test access: DfT architecture (incl. IEEE P1838) and optimizations

00:00M06.2.23D cost flow modeling (with case studies)