M05 Wireless NoC as Interconnection Backbone for Multicore Chips: Promises, Challenges, and Recent Developments

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Date: 
2014-03-24
Time: 
09:30-13:00
Location / Room: 
Konferenz 6

Organisers

Partha Pratim Pande, Washington State University, US
Radu Marculescu, Carnegie Mellon University, US

Speakers

Radu Marculescu, Carnegie Mellon University, US
Partha Pratim Pande, Washington State University, US
Deukhyoun Heo, Washington State University, US
Hiroki Matsutani, Keio University, JP

Description

Continuing progress and integration levels in silicon technologies make possible complete end-user systems consisting of extremely high number of cores on a single chip targeting either embedded or high-performance computing. However, without new approaches for energy- and thermally-efficient design, as well as scalable, low power and high bandwidth on-chip communication architectures, this vision may remain a pipe dream. Towards this end, wireless Network-on-Chip (WiNoC) represents an emerging paradigm for designing low power, high bandwidth interconnect infrastructure for multicore chips. This tutorial will provide a timely and insightful journey into various challenges and emerging solutions of designing WiNoC architectures from a variety of different perspectives, ranging from very high levels of abstraction (e.g., system architecture) to very low levels (e.g., on-chip antenna and transceiver design). The tutorial will start by discussing the fundamentals of network-based communication for 2D and 3D multicore systems and advanced design techniques for multi-domain clock and power management for embedded and high-performance processors, using real examples of multicore platforms. The second part of the tutorial will focus on the design of high bandwidth and low power WiNoC architectures incorporating the small-world effects. We will present detailed performance evaluation and necessary design trade-offs for the small-world WiNoCs with respect to their conventional wireline counterparts. We will conclude this part of the tutorial by presenting design of on-chip millimeter (mm)-wave wireless link as the suitable physical layer for the WiNoCs. In the last part, we will complement the above discussions regarding planar WiNoCs by introducing the wireless 3D NoCs that use inductive coupling though-chip interfaces (TCIs) to connect stacked chips by square coils as data transmitters. We will present design and implementation of wireless 3D NoC systems, real-chip experimental results, and their interconnection techniques. By scope and contents, this tutorial targets students and researchers belonging to both academia and industry.

Agenda

Agenda

TimeLabelSession
09:30M05.1Session 1
00:00M05.1.1Foundations of On-chip Communication: Performance and Power Management in 2D and 3D Multicore Platforms
Radu Marculescu, ,

00:00M05.1.2WiNoC: Network Architecture and Communication Resource Management
Partha Pratim Pande, ,

11:30M05.2Session 2
00:00M05.2.1Millimeter-Wave Wireless Link: The Physical Layer Design for WiNoCs
Deukhyoun Heo, ,

00:00M05.2.13D WiNoC Architectures
Hiroki Matsutani, ,

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