M04 Dynamic Heterogeneous Architectures to Address The Efficiency Crisis!

Printer-friendly versionPDF version
Location / Room: 
Konferenz 4


Houman Homayoun, George Mason University, US (Contact Houman Homayoun)
Farhang Yazdani, BroadPak Corporation, US (Contact Farhang Yazdani)
Ayse Coskun, Boston University, US (Contact Ayse Coskun)
Hank Hoffmann, University of Chicago, US (Contact Hank Hoffmann)


The microprocessor industry is at a crossroads. While it continues to scale performance with each generation, we continue to drive this critically important technology domain. When performance scaling stops, microprocessors become a generic commodity and no longer a technology driver or enabler. Because modern processors are most heavily constrained by power, and sometimes energy, constraints, performance scaling no longer falls naturally from increased transistor counts. Instead, total performance is maximized by maximizing performance/Watt. Future computing platforms will need to be flexible, scalable, conservative on power, while saving size, weight, energy, etc. In addressing these challenges, microprocessor industry is moving towards heterogeneous architecture design. Heterogeneous designs promise to push the envelope of power efficiency further by enabling general purpose processors to achieve the efficiency of customized cores. By enabling more diverse designs, and designs that are customized dynamically, we can push the efficiency envelope even further. This tutorial first reviews the major challenges facing semiconductor industry; in general performance, power, temperature and reliability, and in specific dark and unreliable silicon. The tutorial then introduces the concept of heterogeneous architecture to address the efficiency crisis and briefly reviews the state of the art in static and dynamic heterogeneous architectures in industry and academia. The tutorial then presents 3D design concept and argue how it can eliminate the fundamental barrier to dynamic heterogeneity. Finally it reviews the state of the art in simulators and modeling tools and how they can be integrated to accurately model performance, power, area, and temperature in 3D heterogeneous architectures. About the Team: The team consists of experts in interdisciplinary areas including heterogeneous architecture and 3D design (Houman Homayoun), temperature-aware design, DRAM and 3D integration (Ayse Coskun), 3D fabrication and packaging (Farhang Yazdani), and system architecture design (Hank Hoffman). The team consists of three faculties and one industry expert in the field. Houman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University.



09:30M04.1Session 1
00:00M04.1.1Reviews of major challenges facing semiconductor industry, introduce the concept of dynamic heterogeneous architecture and concept of core pooling (Houman Homayoun)
Houman Homayoun, ,

00:00M04.1.2Pathfinding methodology for optimal design and integration of 2.5D/3D heterogeneous systems
Farhang Yazdani, ,

11:30M04.2Session 2
00:00M04.2.13D systems as platforms for "flexible heterogeneity", cache/memory pooling, power & temperature challenges
Ayse Coskun, ,

00:00M04.2.2Managing dynamically configurable systems: optimizing energy under performance constraints; Coordinating adaptation across the system stack
Hank Hoffman, ,