Topic: T4 Test Access, Design-for-Test, Test Compression, System Test

Design-for-test, -debug, and -manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DfT techniques, DfT for secure systems, DfT economics. Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; testing 3D (TSV-based) chips; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor based test; infrastructure IP; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies.

Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

Co-Chair: Rohit Kapur, Synopsys, US, Contact

Members:

• Davide Appello, ST Microelectronics, IT, Contact
• Luigi DILILLO, LIRMM, FR, Contact
• Marie-Lise Flottes, LIRMM, FR, Contact
• Peter Harrod, ARM Ltd, UK, Contact
• Paolo PRINETTO, Politecnico di Torino, IT, Contact
• Nur Touba, University of Texas at Austin, US, Contact
• Jerzy Tyszer, Poznan University of Technology, PL, Contact
• Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact