Topic: T2 Test Generation, Simulation, and Diagnosis

Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs.

Chair: Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact

Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

Members:

• , Contact
• Nicola Nicolici, McMaster University, CA, Contact
• Frank Poehl, Intel, DE, Contact
• matteo sonza reorda, politecnico di torino - DAUIN, IT, Contact
• Arnau Virazel, LIRMM / Univ. Montpellier, FR, Contact
• Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact