Topic: D13 Physical Design and Verification

Floorplanning; automatic place and route; module generation; design rule checking and layout characterization; electrical verification; problems in deep sub-micron and high-speed design; interconnect-driven and performance-driven layout; process technology developments; design for manufacturability.

Chair: Ralph Otten, TU Eindhoven, NL, Contact

Co-Chair: Azadeh Davoodi, University of Wisconsin - Madison, US, Contact

Members:

• Cheng-Kok Koh, Purdue University, US, Contact
• Jens Lienig, Technical University of Dresden, DE, Contact
• Michael Orshansky, University of Texas at Austin, US, Contact
• Sven Peyer, IBM, DE, Contact
• Jose Pineda, NXP / TU Eindhoven, NL, Contact
• Carl Sechen, UT Dallas, US, Contact
• Rasit Topaloglu, IBM US, US, Contact
• Evangeline Young, The Chinese University of Hong Kong, HK, Contact