W5 3D Integration - Applications, Technology, Architecture, Design, Automation, and Test
Workshop Description
3D Integration is a promising technology for extending Moore's momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. To produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.
The last four editions of this workshop took place in conjunction with DATE 2009 to DATE 2012.
- DATE 2009, Nice, France (https://www.date-conference.com/date09/conference/workshop-W5),
- DATE 2010, Dresden, Germany (https://www.date-conference.com/date10/conference/workshop-W5),
- DATE 2011, Grenoble, France (https://www.date-conference.com/date11/conference/workshop-W5).
- DATE 2012, Dresden, Germany (https://www.date-conference.com/date12/conference/session/W5).
The call for papers (CFP) for the upcoming workshop to be held in conjunction with DATE 2013 is available here.
Topic Areas
You are invited to participate and submit your contributions to the DATE 2013 Friday Workshop on 3D Integration. The areas of interest include (but are not limited to) the following topics:
- 3D technologies: chip-on-chip, micro-bumping, contactless, and through-silicon-vias interconnect
- TSV formation, perm./temp. wafer (de-)bonding
- 3D architectures and design space exploration
- 3D combinations of logic, memory, analog, RF
- Application, product, or test chip case studies
- 3D design methods and EDA tools
- Signal and power integrity, and ESD in 3D
- Thermo(-mechanical) analysis and -aware design
- Chip-package co-design for 3D
- Test, design-for-test, and debug techniques for 3D
- Wafer test access, KGD test, thin-wafer handling
- Economic benefit/cost trade-off studies
- Standardization initiatives
Submission Instructions
Submissions are invited in the form of (extended) abstracts not exceeding two pages. Submissions must be sent in as PDF file via the Welcome paper submission system: http://welcome.molesystems.com/DATE13-3D-WS/2013/. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, and technical soundness. Selected submissions can be accepted for regular or poster presentation. At the workshop, an Electronic Workshop Digest will be made available to all workshop participants, which will include all material that authors are willing to provide: abstract, paper, slides, poster, etc.
| Paper Submission deadline | November 25, 2012 |
| Notification of Acceptance | December 10, 2012 |
| Camera-Ready Material due date | February 22, 2013 |
The workshop program contains the following elements.
- One invited keynote address
- Two invited talk
- Two sessions with in total eight regular presentations
- Two poster sessions
- One panel session
Agenda
Agenda
| Time | Label | Session |
|---|---|---|
| 08:30 | W5.1 | Session 1: Opening Moderator: |
| 08:30 | W5.1.1 | Welcome Address Qiang Xu, The Chinese University of Hong Kong, HK |
| 08:40 | W5.1.2 | Keynote Address: 3D IC Design and CAD Research: Challenges and Opportunities Sung Kyu Lim, Georgia Tech, US |
| 09:25 | W5.1.3 | Invited Talk: 3D IC Test Challenges and Solutions Erik Jan Marinissen, IMEC, BE |
| 10:00 | W5.2 | Session 2: Posters Posters - coffee + tea break |
| 10:00 | A NOVEL ON-CHIP TSV-BASED BANDPASS FILTER DESIGN Khaled MOHAMED, Mentor Graphics, EG | |
| 10:00 | EXPLICIT AND UNCONDITIONALLY STABLE METHOD FOR THE FAST 3-D SIMULATION OF STAKED CHIP POWER DISTRIBUTION NETWORKS CONNECTED BY THROUGH SILICON VIA ARRAYS Tadatoshi SEKINE and Hideki ASAI, Shizuoka University, JP | |
| 10:00 | LAYOUT-TECHNOLOGY INTERACTIONS AND OPTIMIZATION OF INTERPOSER BASED DESIGNS Andy HEINIG and Uwe KNOECHEL, Fraunhofer IIS/EAS, DE | |
| 10:00 | PHYSICALLY BASED APPROACH OF SIMPLE COMPACT MODELING FOR 3D INTERCONNECT IN RF CIRCUITS Fengyuan SUN1, Jean-Etienne LORIVAL1, Francis CALMON1 and christian GONTRAND2 1INL, FR; 2INSA/INL, FR | |
| 10:00 | MODELING OF 3D-IC FABRICATION STEP SEQUENCES Armin GRUENEWALD, Kai HAHN and Rainer BRüCK, University of Siegen, DE | |
| 10:00 | TSV INTERPOSER FOR 3D WAFER LEVEL SYSTEM IN PACKAGES M. Jürgen WOLF, Fraunhofer IZM, DE | |
| 10:00 | A NEW TSV TEST METHOD WITH BISECTION huiyun LI, Shenzhen Institutes of Advanced Technology, CN | |
| 10:00 | WIOMING, A LOW POWER WIDEIO COMPATIBLE 3D CIRCUIT Denis Dutoit, Pascal Vivet and Alexandre Valentian, CEA, FR | |
| 10:00 | ANALYZING 3D NOC OCCUPANCY AND LATENCY Yan GHIDINI, Matheus MOREIRA, Thais WEBBER, Ney CALAZANS and Cesar MARCON, PUCRS, BR | |
| 10:30 | W5.3 | Session 3: Design, Manufacturing and Test of 3D-Ics Moderator: |
| 10:30 | W5.3.1 | Silicon Interposers with Through Silicon Vias - A Base Approach for 3D Wafer Level System Integration Kai Zoschke1, Rene Puschmann1, Oswin Ehrmann2, Juergen Wolf1 and Klaus-Dieter Lang2 1Fraunhofer IZM, DE; 2Technical U of Berlin, DE |
| 10:53 | W5.3.2 | Thermal-aware Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chips Xiaohang Wang1, Mei Yang2, Yingtao Jiang2, Maurizio Palesi3 and Terrence Mak4 1Guangzhou Ins. of Adv. Tech., CN; 2U of Nevada, US; 3Kore U, IT; 4The Chinese University of Hong Kong, HK |
| 11:15 | W5.3.3 | 3D MPSoC Design Using 2D EDA tools: Analysis of Parameters Mohamad Jabbar1, Abir M’Zah2, Omar Hammami2 and Dominique Houzet3 1GIPSA-Lab/ENSTA Paristech, FR; 2ENSTA Paristech, FR; 3GIPSA-Lab, FR |
| 11:38 | W5.3.4 | Pre-bond Test of TSVs in 3D SICs using Ring Oscillators Yassine Fkih1, Pascal Vivet2, Bruno Rouzeyre3, Marie-lise Flottes3 and Giorgio Di Natale3 1CEA-Leti / LIRMM U Montpellier II, FR; 2CEA-Leti, FR; 3LIRMM U Montpellier II, FR |
| 12:00 | W5 | Lunch Break Buffet meal |
| 13:00 | W5.4 | Session 4: Performance, Reliability and Cost Modelling of 3D Ics Moderator: |
| 13:00 | W5.4.1 | MoNICA: A Performance- and Thermal-Aware Floorplan Tool for Heterogeneous 3D NoC-based MPSoCs Felipe Frantz1, da Silva Matos2, Lioua Labrak1, Fabien Clermidy3, Ian O’Connor1, Luigi Carro2 and Altamiro Susin2 1Lyon Institute of Nanotechnology, FR; 2Federal U of Rio Grande do Sul, BR; 3CEA-Leti, FR |
| 13:23 | W5.4.2 | Short-Circuit Current Free NEMFET Based Logic and NEMFET-MOS Hybrid 3D Memory Marius Enachescu, Mihai Lefter, George Razvan Voicu and Sorin D. Cotofana, Delft U of Tech., NL |
| 13:45 | W5.4.3 | 3D-COSTAR: A Cost Model for 3D Stacked Ics Mottaqiallah Taouil1, Said Hamdioui1, Erik Jan Marinissen2 and Sudipta Bhawmik3 1Delft U of Tech., NL; 2IMEC, BE; 3Qualcomm, US |
| 14:08 | W5.4.4 | WIOMING, a Low Power Wide IO compatible 3D circuit Denis Dutoit, Pascal Vivet and Alexandre Valentian, CEA, FR |
| 14:30 | W5.5 | Session 5: Posters Posters - coffee + tea break |
| 14:30 | A NOVEL ON-CHIP TSV-BASED BANDPASS FILTER DESIGN Khaled MOHAMED, Mentor Graphics, EG | |
| 14:30 | EXPLICIT AND UNCONDITIONALLY STABLE METHOD FOR THE FAST 3-D SIMULATION OF STAKED CHIP POWER DISTRIBUTION NETWORKS CONNECTED BY THROUGH SILICON VIA ARRAYS Tadatoshi SEKINE and Hideki ASAI, Shizuoka University, JP | |
| 14:30 | LAYOUT-TECHNOLOGY INTERACTIONS AND OPTIMIZATION OF INTERPOSER BASED DESIGNS Andy HEINIG and Uwe KNOECHEL, Fraunhofer IIS/EAS, DE | |
| 14:30 | PHYSICALLY BASED APPROACH OF SIMPLE COMPACT MODELING FOR 3D INTERCONNECT IN RF CIRCUITS Fengyuan SUN1, Jean-Etienne LORIVAL1, Francis CALMON1 and christian GONTRAND2 1INL, FR; 2INSA/INL, FR | |
| 14:30 | MODELING OF 3D-IC FABRICATION STEP SEQUENCES Armin GRUENEWALD, Kai HAHN and Rainer BRüCK, University of Siegen, DE | |
| 14:30 | TSV INTERPOSER FOR 3D WAFER LEVEL SYSTEM IN PACKAGES M. Jürgen WOLF, Fraunhofer IZM, DE | |
| 14:30 | A NEW TSV TEST METHOD WITH BISECTION huiyun LI, Shenzhen Institutes of Advanced Technology, CN | |
| 14:30 | WIOMING, A LOW POWER WIDEIO COMPATIBLE 3D CIRCUIT Denis Dutoit, Pascal Vivet and Alexandre Valentian, CEA, FR | |
| 14:30 | ANALYZING 3D NOC OCCUPANCY AND LATENCY Yan GHIDINI, Matheus MOREIRA, Thais WEBBER, Ney CALAZANS and Cesar MARCON, PUCRS, BR | |
| 15:00 | W5.6 | Session 6: Invited Talk Moderator: |
| 15:00 | W5.6.1 | Expanding the Design-Manufacturing Interface for 3D IC Juan Rey, Mentor Graphics, US |
| 15:40 | W5.7 | Session 7: Panel Discussion Moderator: |
| Panelists: Panelists: Paul Franzon1, Georg Kimmich2, Juan Rey3, Ravi Varadarajan4 and Milojevic Dragomir5 1University North Carolina, US; 2STEricsson, FR; 3Mentor Graphics, US; 4Atrenta, FR; 5IMEC, BE | ||
| 16:40 | W5.8 | Close |
