F Post-Silicon Validation: Old Challenges and New Solutions

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Agenda

Agenda

TimeLabelSession
09:30F.1Session 1
09:30Post-silicon bugs and industry tools
Rand Gray1 and Wisam Kadry2
1Intel Corp, US; 2IBM, IL

11:00FCoffee Break

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.
11:30F.2Session 2
11:30Post-silicon monitoring infrastructures
Valeria Bertacco1 and Sharad Malik2
1University of Michigan, US; 2Princeton University, US

13:00FM1Challenges in Design and Qualification for Automotive Electronics

Organisers:
Michael Nicolaidis, TIMA / IMAG, FR
Rubin Parekhji, Texas Instruments, IN


This is a focused meeting on design and qualification challenges for electronic circuits used in automotive systems. It will be conducted in free format, where practitioners and experts will share state-of-the-art practices and user experiences, and discuss new challenges in this area. Topics likely to be covered include adoption of automotive safe standards, compliance checks and certification processes, IC component vs overall system reliability, time zero screens vs life time failure estimation, firmware qualification and co-design requirements.
13:00FLunch Break

Buffet meal
14:30F.3Session 3
14:30Bug localization. Microprocessor's solutions
Valeria Bertacco1 and Sharad Malik2
1University of Michigan, US; 2Princeton University, US

16:00FCoffee Break

Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.
16:30F.4Session 4
16:30Post-silicon methodologies in the industry
Rand Gray1 and Wisam Kadry2
1Intel Corp, US; 2IBM, IL

19:00FM2ACM SIGDA / EDAA PhD Forum

PhD Forum Committee Chair:
Peter Marwedel, TU Dortmund, DE

PhD Forum Committee Members:
Walter Anheier, University of Bremen, DE
M. Balakrishnan, Indian Institute of Technology Delhi, IN
Davide Bertozzi, University of Bologna, IT
Joan Figueras, Univ. Politècnica de Catalunya, Barcelona, ES
Helmut Graeb, TU München, DE
Jörg Henkel, KIT, DE
Gi-Joon Nam, IBM Austin, US
Ulrich Rückert, Bielefeld University, DE
Jeonghee Shin, IBM T.J. Watson Research Center, US
Sander Stuijk, TU Eindhoven, NL
Miroslav Velev, Aries Design Automation, US
Norbert Wehn, TU Kaiserslautern, DE


The ACM SIGDA / EDAA PhD forum is part of the DATE Conference and hosted by ACM SIGDA and the European Design Automation Association (EDAA). It offers the opportunity for PhD students to present their thesis work to a broad audience in the design, automation and test community from academia and industry. During the presentation at the DATE Conference, it helps students to establish contacts. Also, representatives from industry and academia get a glance of state-of-the-art research in design, automation and test. The review process resulted in the selection of the PhD students listed below. We thank ACM SIGDA, EDAA, and DATE for making this Forum possible.

Peter Marwedel (Chair, ACM SIGDA / EDAA PhD Forum at DATE 2013)

19:00PhD.1Energy Consumption Information in High-level Models
Laurent Bousquet, Tima Laboratory, Grenoble, FR

19:00PhD.2OpenMP extensions to Exploit HW Acceleration on Shared-Memory Many-Core Clusters
Paolo Burgio, University of Bologna, IT

19:00PhD.3Out-of-order Parallel Simulation for Electronic System-Level Design
Weiwei Chen, UC Irvine, US

19:00PhD.4On Efficient Management of Flash Memory for Long Lifetime and High Performance
Wang Chundong, National University of Singapore, SG

19:00PhD.6A Resilient Framework for Post-Silicon Delay Validation of High Performance Circuits
Prasanjeet Das, University of Southern California, US

19:00PhD.7Self-adaptivity of Applications on Network on Chip Multiprocessors: The Case of Fault-Tolerant Kahn Process Networks
Onur Derin, University of Lugano, CH

19:00PhD.8Modeling and Synthesis of the Network in Distributed Embedded Systems
Emad Ebeid, University of Verona, IT

19:00PhD.9Path-based Partitioning Methods for 3D NoCs with Minimal Adaptive Routing
Masoumeh Ebrahimi, University of Turku, FI

19:00PhD.10Architectural Exploration Methods and Tools for Heterogeneous 3D-IC
Felipe F. Ferreira, Lyon Institute of Nanotechnology, FR

19:00PhD.11Working With Adaptive NoC Routers
John Jose, IIT Madras, IN

19:00PhD.12Energy-Aware Multi-Threaded Software Systems: An Overview
Steve Kerrison, University of Bristol, UK

19:00PhD.13On Optimizing Dynamic Memory Allocators
Ioannis Koutras, National Technical University of Athens, GR

19:00PhD.14FPGA-based Hardware Accelerators for Embedded Object Detection Systems
Christos Kyrkou, University of Cyprus, CY

19:00PhD.15Built In Self Test of Pipeline Analog-to-Digital Converters
Asma Laraba, Tima Laboratory,Grenoble, FR

19:00PhD.16Automated Techniques for Verification-driven Design at the Electronic System Level
Hoang Le, University of Bremen, DE

19:00PhD.17High-Speed Interconnect Models with Stochastic Parameter Variability
Paolo Manfredi, Politecnico di Torino, IT

19:00PhD.18Microarchitectures for Hybrid High and Ultra-low Voltage Operation
Bojan Maric, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES

19:00PhD.19Design Entropy
Benjamin Menhorn, Ulm University, DE

19:00PhD.20Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits
Srobona Mitra, IBM India Pvt Ltd, IN

19:00PhD.21Assertions: From a Mixed-Signal Perspective
Subhankar Mukherjee, IIT Kharagpur, IN

19:00PhD.22Towards Optimized Flexible Multi-ASIP Architectures for LDPC/Turbo Decoding
Purushotham Murugappa, Telecom Bretagne, FR

19:00PhD.23Performance Analysis of Complex Real-Time Applications on Multi-Core Systems with Shared Resources
Mircea Negrean, TU Braunschweig, DE

19:00PhD.24Composable Execution of Mixed-Criticality Embedded Applications With Mixed-Models-of-Computation
Ashkan Beyranvand Nejad, Delft University of Technology, NL

19:00PhD.25Composable Application-level Power Management for Real-Time Embedded Systems
Andrew Nelson, Delft University of Technology, NL

19:00PhD.26RSSI-based Localisation of Mobile Robots With Online Channel Estimation
Luis Olivera, University of Porto, PT

19:00PhD.27Improving Performance of FPGAs Using Resistive Switching Memory (RRAM) Based Low Power Circuit Architectures
Santhosh Onkaraiah, CEA-Leti, Minatec, FR

19:00PhD.28Capacity Metric for Chip Heterogeneous Multiprocessors
Mwaffaq Otoom, Yarmouk University, JO

19:00PhD.29System-Level Approaches for Fixed-Point Refinement of Signal Processing Algorithms
Karthik Parashar, INRIA Bretagne Atlantique, Rennes, FR

19:00PhD.30Model Checking Memory-Related Properties of SystemC Transaction Level Designs
Marcel Pockrandt, TU Berlin, DE

19:00PhD.31Soft Error Mitigation in Asynchronous Networks on Chip
Julian Pontes, Universidade Católica do Rio Grande do Sul, BR

19:00PhD.32A Reconfigurable Low-Latency Architecture for Real-Time Image and Video Processing
Paulo Possa, University of Mons, BE

19:00PhD.33Thread Assignment of Network Applications in Multithreaded Processors: A Statistical Approach
Petar Radojkovic, Barcelona Super Computer Center, ES

19:00PhD.34Reliable Software for Unreliable Hardware
Semeen Rehman, Karlsruhe Institute of Technology, DE

19:00PhD.35Verification of Hybrid DEVS Models
Hesham Saadawi, Carleton University, Ottawa, CA

19:00PhD.36MiMAPT: Adaptive Multi-Resolution Thermal Analysis at RT and Gate Level
Mohammadsadegh Sadri, University of Bologna, IT

19:00PhD.38Variability, Regularity and DFM Metrics
Kasyab Parmesh Subramaniyan, Chalmer University, SE

19:00PhD.40Disparity Estimation Hardware Architectures and Design Techniques for Embedded Stereo Vision Applications
Christos Ttofis, University of Cyprus, CY

19:00PhD.42Low Power and High Performance Current Mode On-Chip Interconnect System Design and Optimization
Xinsheng Wang, Harbin Institute of Technology, Harbi, CN

13:00FM3IEEE European Test Technology Technical Council (ETTTC) Meeting

Organiser:
Matteo Sonza Reorda, Politecnico di Torino, IT

18:30FM4EDAA General Assembly

Organiser:
Georges Gielen, Katholieke Universiteit Leuven, BE

18:30FM527. European SystemC Users' Group Meeting

Organiser:
Axel Braun, European SystemC Users' Group & University of Tuebingen, DE


The European SystemC Users' Group (ESCUG) announces its 27th meeting at DATE Conference 2013 on Tuesday, March 19th, 2013, 18:30 h (closing 21:30 h). The 27th European SystemC Users' Group Meeting encompasses not only SystemC but the wider picture of Accellera standards and technologies, such as UVM, SystemVerilog, SVA, and IP-XACT. This meeting will be organized in town hall style, giving experts from Accellera a platform to introduce these design and verification technologies and providing the audience an opportunity to join interesting discussion.

Please register here.

We're looking forward to meeting you in Grenoble!

18:30FM1.1Opening and Welcome
Oliver Bringmann, University of Tuebingen, DE

18:45FM1.2Accellera News Update
Dennis Brophy, Accellera Systems Initiative, US

19:15FM1.3Accellera Systems Initiative Presentstion
Dennis Brophy1, Martin Barnasconi2 and Laurent Maillet-Contoz3
1Accellera Systems Initiative, US; 2Accellera Systems initiative, NL; 3Accellera Systems Initiative, FR

20:15FM1.4Interactive Discussion

21:15FM1.5Wrap-Up and Closing
Oliver Bringmann, University of Tuebingen, DE

 

Groups: