Topic: D8 Network on Chip

Architecture, modelling and design techniques for network on chip; design methods for the on-chip interconnection network: interconnect topology, switching, routing and flow control methods; architecture and design for fault-tolerance, reliability enhancement, quality of service, dynamic voltage and frequency scaling; techniques and methodologies for NoC testing; GALS synchronization architectures for networks-on-chip; physical design techniques and methodologies; hardware/software communication abstraction, component-based modelling, platform-based design and methodologies, NoC design space exploration frameworks; programming models for NoC-based platforms; design of on-chip networks based on alternative technologies such as photonics/optics, wireless, 3D stacking.

Chair: Davide Bertozzi, University of Ferrara, IT, Contact

Co-Chair: Federico Angiolini, iNoCs, CH, Contact

Members:

• Paul Ampadu, University of Rochester, US, Contact
• David Atienza, EPFL, CH, Contact
• Luca Benini, Università di Bologna, IT, Contact
• Luca Carloni, Columbia University, US, Contact
• Érika Cota, UFRGS, BR, Contact
• jflichdisca [dot] upv [dot] es, Contact
• k [dot] g [dot] w [dot] goossenstue [dot] nl, Contact
• hessabisharif [dot] edu, Contact
• Axel Jantsch, KTH, SE, Contact
• Jung Ho Ahn, Seoul National University, KR, Contact
• Hiroki Matsutani, Keio University, JP, Contact
• , Contact
• Steven Nowick, Columbia University, US, Contact
• Pascal VIVET, CEA-LETI, FR, Contact
• Sungjoo Yoo, POSTECH, KR, Contact