Technical Programme Committee 2012

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Track D: Design, Methods and Tools (click to open)

addressing design automation and design tools for electronic and embedded systems. Emphasis is on methods and tools related to the use of computers in designing products. This includes designer feedback on existing design methods and tools as well as to initiate discussions on requirements of future system architectures, design flows and environments.

Track Chair: , Contact

Topics

D1 System Specifications, Models and Methodologies (click to open)

Chair: Andy Pimentel, University of Amsterdam, NL, Contact

Co-Chair: Dominique Borrione, TIMA Labs, FR, Contact

Topic Members (click to open)

  • Andreas Gerstlauer, University of Texas at Austin, US, Contact
  • Jan Haase, Technical University Vienna, AT, Contact
  • Christian Haubelt, University of Erlangen, DE, Contact
  • Wolfgang Mueller, Universität Paderborn, DE, Contact
  • Ingo Sander, Royal Institute of Technology, SE, Contact
  • Leandro Indrusiak, University of York, UK, Contact
  • Sander Stuijk, Eindhoven University of Technology, NL, Contact
  • Eugenio Villar, University of Cantabria, ES, Contact

Modeling and specification methodologies for complex, HW-SW embedded systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

D2 System Design, Synthesis and Optimization (click to open)

Chair: jamaatdtu [dot] dk, Contact

Co-Chair: Luciano Lavagno, Politecnico di Torino, IT, Contact

Topic Members (click to open)

  • Soonhoi Ha, Seoul National University, KR, Contact
  • wido [dot] kruijtzeratsynopsys [dot] com, Contact
  • Sri Parameswaran, UNSW, AU, Contact
  • Sudeep Pasricha, Colorado State University, US, Contact
  • donatella [dot] sciutoatpolimi [dot] it, Contact
  • Todor Stefanov, Leiden University, NL, Contact
  • Jürgen Teich, University of Erlangen-Nuremberg, DE, Contact
  • jasonxueatcityu [dot] edu [dot] hk, Contact

Synthesis of complete systems, application- and domain-specific synthesis techniques; system-level models for design, optimization and synthesis; hardware/software co-design and partitioning issues; hardware/software interface and communication synthesis; interface-based and correct-by construction designs; system-level scheduling techniques; protocol synthesis and optimization; system optimization for all cost functions (timing, electrical, non-functional); multi-objective, classical and nature-inspired optimization techniques for system level design; large-scale and industrial case studies involving full system optimization and synthesis.

D3 Simulation and Validation (click to open)

Chair: Valeria Bertacco, University of Michigan, US, Contact

Co-Chair: Franco Fummi, Universita' di Verona, IT, Contact

Topic Members (click to open)

  • Andrea Acquaviva, Politecnico di Torino, IT, Contact
  • Pallab Dasgupta, Indian Institute of Technology Kharagpur, IN, Contact
  • Rand Gray, Intel Corporation, US, Contact
  • Daniel Grosse, University of Bremen, DE, Contact
  • Ian Harris, University of Californa Irvine, US, Contact
  • Michael Hsiao, Virginia Tech, US, Contact
  • Florian Letombe, SpringSoft, FR, Contact
  • Prabhat Mishra, University of Florida, US, Contact
  • Ronny Morad, IBM Research - Haifa, IL, Contact
  • Pablo Sanchez, University of Cantabria, ES, Contact
  • Jaan Raik, Tallinn University of Technology, Department of Computer Engineering, EE, Contact
  • Shireesh Verma, Conexant Systems Inc., US, Contact
  • Mark Zwolinski, University of Southampton, UK, Contact

Simulation-based verification; post-silicon validation; hardware/software co-simulation and validation, ATPG for validation; transaction-level validation; semi-formal verification techniques; testbench generation; design error debug and diagnosis; advanced simulation and emulation techniques from system to circuit level; simulation accelerators; multi-domain simulation techniques for mixed systems.

D4 Design of Low Power Systems (click to open)

Chair: tudor [dot] murganatintel [dot] com, Contact

Co-Chair: Domenik Helms, OFFIS, DE, Contact

Topic Members (click to open)

  • Naehyuck Chang, Seoul National University, KR, Contact
  • Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
  • Wei Huang, IBM Research, US, Contact
  • acojimatimse [dot] cnm [dot] es, Contact
  • Marisa Lopez-Vallejo, UPM, ES, Contact
  • Alberto Macii, Politecnico di Torino, IT, Contact
  • biswajit [dot] mishraatepfl [dot] ch, Contact
  • Alberto Nannarelli, DTU, DK, Contact
  • Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
  • Wolfgang Nebel, OFFIS and University of Oldenburg, DE, Contact
  • , Contact
  • Mircea Stan, University of Virginia, US, Contact

Design methods, techniques and case studies of low power systems, covering aspects from specification, mapping, new algorithms, system architecture to circuit; including power minimization techniques for analog and digital circuits, HW and SW aspects, power management, batteries, energy harvesting, thermal aware computation and technology aware design aspects in nanometer technologies (i.e., leakage, variability, reliability, 3D stacking, etc.).

D5 Power Estimation and Optimization (click to open)

Chair: Massimo Poncino, Politecnico di Torino, IT, Contact

Co-Chair: jian-jia [dot] chenatkit [dot] edu, Contact

Topic Members (click to open)

  • Edith Beigne, CEA-LETI Minatec, FR, Contact
  • Yiran Chen, Seagate Technology, US, Contact
  • William Fornaciari, Politecnico di Milano - DEI, IT, Contact
  • josef [dot] haidatinfineon [dot] com, Contact
  • Joerg Henkel, Karlsruhe Institute of Technology, DE, Contact
  • Mauro Olivieri, Sapienza University of Rome, IT, Contact
  • raghunathanatpurdue [dot] edu, Contact
  • ranga [dot] vemuriatuc [dot] edu, Contact
  • Chia-Lin Yang, National Taiwan University, TW, Contact

Algorithms, techniques and tools for power and temperature modeling, estimation and optimization of electronic systems applicable at all levels of the design hierarchy, from system-level specification to layout, including software and run-time management.

D6 Emerging Technologies, Systems and Applications (click to open)

Chair: yuanxieatcse [dot] psu [dot] edu, Contact

Co-Chair:

Topic Members (click to open)

  • siddharth [dot] j [dot] gargatgmail [dot] com, Contact
  • Hai Li, Polytechnic Institute of New York University, US, Contact
  • dmilojevatulb [dot] ac [dot] be, Contact
  • , Contact
  • Chrysostomos Nicopoulos, University of Cyprus, CY, Contact
  • Micahel Niemier, University Of Notre Dame, US, Contact
  • Yvain Thonnart, CEA, LETI, MINATEC, FR, Contact
  • Chun-Yao Wang, National Tsing Hua University, TW, Contact
  • yu-wangatmail [dot] tsinghua [dot] edu [dot] cn, Contact

System design methods, models of computation, and case studies for emerging applications: ambient intelligence, ubiquitous computing, wearable computing, sensor networks, bio-inspired computation; Design automation flows and case studies for upcoming and future technologies: MEMS, BIOMEMS, Lab-on-a-chip, 3D integration, nanoscale and molecular scale circuits and systems.

D7 Formal Methods and Verification (click to open)

Chair: Wolfgang Kunz, University of Kaiserslautern, DE, Contact

Co-Chair: Gianpiero Cabodi, Politecnico di Torino, IT, Contact

Topic Members (click to open)

  • biereatjku [dot] at, Contact
  • roderick [dot] bloematiaik [dot] tugraz [dot] at, Contact
  • Alessandro Cimatti, FBK-irst (Fondazione Bruno Kessler - Center for Information technology), IT, Contact
  • Joao Marques-Silva, University College Dublin, IE, Contact
  • Fahim Rahim, Atrenta, FR, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem-proving, abstraction and refinement techniques, and real time verification); technologies supporting formal verification (including SMT, SAT, BDD, ATPG, and related work); semi-formal verification techniques; applications and case studies; formal verification of IPs, SoCs, cores and real-time/embedded systems; verification in practice, namely the integration of verification into the design flow.

D8 Network on Chip (click to open)

Chair: Davide Bertozzi, University of Ferrara, IT, Contact

Co-Chair: Federico Angiolini, iNoCs, CH, Contact

Topic Members (click to open)

  • Paul Ampadu, University of Rochester, US, Contact
  • David Atienza, EPFL, CH, Contact
  • Luca Benini, Università di Bologna, IT, Contact
  • Luca Carloni, Columbia University, US, Contact
  • Érika Cota, UFRGS, BR, Contact
  • jflichatdisca [dot] upv [dot] es, Contact
  • k [dot] g [dot] w [dot] goossensattue [dot] nl, Contact
  • hessabiatsharif [dot] edu, Contact
  • Axel Jantsch, KTH, SE, Contact
  • Jung Ho Ahn, Seoul National University, KR, Contact
  • Hiroki Matsutani, Keio University, JP, Contact
  • , Contact
  • Steven Nowick, Columbia University, US, Contact
  • Pascal VIVET, CEA-LETI, FR, Contact
  • Sungjoo Yoo, POSTECH, KR, Contact

Architecture, modelling and design techniques for network on chip; design methods for the on-chip interconnection network: interconnect topology, switching, routing and flow control methods; architecture and design for fault-tolerance, reliability enhancement, quality of service, dynamic voltage and frequency scaling; techniques and methodologies for NoC testing; GALS synchronization architectures for networks-on-chip; physical design techniques and methodologies; hardware/software communication abstraction, component-based modelling, platform-based design and methodologies, NoC design space exploration frameworks; programming models for NoC-based platforms; design of on-chip networks based on alternative technologies such as photonics/optics, wireless, 3D stacking.

D9 Architectural and Microarchitectural Design (click to open)

Chair: laura [dot] pozziatusi [dot] ch, Contact

Co-Chair: Tulika Mitra, National University of Singapore, SG, Contact

Topic Members (click to open)

  • Todd Austin, University of Michigan, US, Contact
  • Mladen Berekovic Mladen Berekovic, TU-BS, DE, Contact
  • Bjorn De Sutter, Ghent University, BE, Contact
  • franklinatcs [dot] ucsb [dot] edu, Contact
  • Nikos Hardavellas, Northwestern University, US, Contact
  • rakeshkatillinois [dot] edu, Contact
  • memikatece [dot] northwestern [dot] edu, Contact
  • Andreas Moshovos, University of Toronto, CA, Contact
  • pnevmatiatics [dot] forth [dot] gr, Contact
  • tsatoatfukuoka-u [dot] ac [dot] jp, Contact
  • Zili Shao, Hong Kong Polytechnic University, HK, Contact
  • Cristina SILVANO, Politecnico di Milano, IT, Contact
  • samiatyehia [dot] eu, Contact

Architectural and microarchitectural design techniques, memory systems, power and energy efficient architectures, multi/many-core architectures, multithreading techniques and support for parallelism, modelling and performance analysis, advanced computer architecture for application-specific applications, special purpose processors and accelerators, arithmetic architectures, future and emerging architectures.

D10 Architectural and High-Level Synthesis (click to open)

Topic Members (click to open)

    Synthesis of hardware systems from high-level descriptions; hardware-centric system-level synthesis, analysis, and optimization; high-level language hardware description, parsing and compilation; scheduling, allocation, and binding of operations, variables, and transfers; automatic design and optimization of datapaths, dedicated memory and communication structures, and controllers; performance, cost, and power driven architectural-level optimizations; application-specific processor generation, automatic processor customization, and accelerator synthesis.

    D11 Reconfigurable Computing (click to open)

    Chair: Fadi Kurdahi, University of California at Irvine, US, Contact

    Co-Chair: Marco Platzner, University of Paderborn, DE, Contact

    Topic Members (click to open)

    • koen bertels, Delft University of Technology, NL, Contact
    • Fabrizio Ferrandi, Politecnico di Milano, IT, Contact
    • diana [dot] goehringeratrub [dot] de, Contact
    • elehyatnus [dot] edu [dot] sg, Contact
    • w [dot] lukatimperial [dot] ac [dot] uk, Contact
    • patrick [dot] lysaghtatxilinx [dot] com, Contact
    • Walid Najjar, UC Riverside, US, Contact
    • Smail Niar, University of Valenciennes, FR, Contact
    • mazen [dot] saghiratqatar [dot] tamu [dot] edu, Contact

    Statically and dynamically reconfigurable and reprogrammable systems and components: platforms and architectures, FPGAs, reconfigurable processors, design methods and tools for reconfigurable computing and communication, applications.

    D12 Logic and Technology Dependent Synthesis (click to open)

    Co-Chair: Sachin Sapatnekar, University of Minnesota, US, Contact

    Topic Members (click to open)

    • Michel Berkelaar, Delft University of Technology, NL, Contact
    • valentina [dot] cirianiatunimi [dot] it, Contact
    • Jordi Cortadella, Universitat Politecnica de Catalunya, ES, Contact
    • Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
    • victor kravets, IBM, US, Contact
    • José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact
    • John Hayes, University of Michigan, US, Contact
    • Tiziano Villa, University of Verona, IT, Contact

    Logic-level optimization, including techniques driven by timing, power, variability, or reliability; combinational and sequential synthesis; technology mapping; controller/FSM synthesis; arithmetic circuits; FPGA synthesis; asynchronous and mixed synchronous/asynchronous circuits; timing analysis for nanometer-scale circuits; combined logic synthesis and layout design; timing closure; logic-level postsilicon performance correction and adaptation.

    D13 Physical Design and Verification (click to open)

    Chair: r [dot] h [dot] j [dot] m [dot] ottenattue [dot] nl, Contact

    Co-Chair: Azadeh Davoodi, University of Wisconsin - Madison, US, Contact

    Topic Members (click to open)

    • Matthew Guthaus, University of California Santa Cruz, US, Contact
    • , Contact
    • Jens Lienig, Technical University of Dresden, DE, Contact
    • Igor Markov, University of Michigan, US, Contact
    • Mustafa Ozdal, Intel, US, Contact
    • Sven Peyer, IBM, DE, Contact
    • Sherief Reda, Brown University, US, Contact
    • tcwangatcs [dot] nthu [dot] edu [dot] tw, Contact

    Floorplanning; automatic place and route; module generation; design rule checking and layout characterization; electrical verification; problems in deep sub-micron and high-speed design; interconnect-driven and performance-driven layout; process technology developments; design for manufacturability.

    D14 Analog and Mixed-Signal Circuits and Systems (click to open)

    Chair: catherine [dot] dehollainatepfl [dot] ch, Contact

    Co-Chair: dundaratboun [dot] edu [dot] tr, Contact

    Topic Members (click to open)

    • pacovatimse-cnm [dot] csic [dot] es, Contact
    • Georges Gielen, Katholieke Universiteit Leuven, BE, Contact
    • Christoph Grimm, TU Vienna, AT, Contact
    • Joachim Haase, Fraunhofer EAS, DE, Contact
    • Lars Hedrich, University of Frankfurt, DE, Contact
    • Tom Kazmierski, University of Southampton, UK, Contact
    • marie-Minerve Louerat, UNiversity Pierre & Marie Curie, LIP6, FR, Contact
    • Dominique MORCHE, CEA-LETI, FR, Contact
    • Alain Vachoux, EPFL, CH, Contact

    CAD for analogue and mixed-signal circuits and systems: Layout, Topology generation, Architecture and System Synthesis, Modelling of AMS circuits and systems, Modelling strategies, Modelling of complex analogue mixed-signal systems, Model generation, Formal and Symbolic Techniques; Languages for AMS circuits and systems: VHDL-AMS, Verilog-AMS, SystemC-AMS, Matlab/Simulink, Ptolomy; Innovative circuit topologies and architectures: Topologies/architectures that increase robustness, Topologies/architectures that increase re-usability; Modelling and Synthesis of Multi-Domain systems: MEMS, Energy Harvesting Systems.

    D15 Interconnect, EMC, EMD and Packaging Modeling (click to open)

    Co-Chair: Stefano Grivet-Talocia, Politecnico di Torino, IT, Contact

    Topic Members (click to open)

    • ielfadelatmasdar [dot] ac [dot] ae, Contact

    Modelling, characterisation and analysis of on and off chip interconnects and packaging; modelling and analysis of noise due to electromagnetic interaction on signal, power/ground and substrate; electromagnetic emission, susceptibility and compatibility.


    Track A: Application Design (click to open)

    is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as innovative design methodologies and applications of specific design technologies. Contributions should illustrate state-of-the-art or record breaking designs, which will provide viable solutions in tomorrow’s silicon and embedded systems. In topic A7, there is the opportunity to submit short, 2-page papers, that relate to industrial research and practice.

    Track Chair: David Atienza, EPFL, CH, Contact

    Topics

    A1 Computing and Green IT Systems (click to open)

    Chair: Tajana Simunic Rosing, UCSD, US, Contact

    Topic Members (click to open)

    • AYSE COSKUN, Boston University, US, Contact
    • paulo [dot] possaatumons [dot] ac [dot] be, Contact
    • Michael Kauschke, Intel GmbH, DE, Contact
    • Christos Kozyrakis, Stanford University, US, Contact
    • Qinru Qiu, Binghamton University, US, Contact

    Practical design experiences in industrial projects or academic projects with high industrial relevance targeting high performance, parallel, or information technology systems with a focus on energy efficiency. Target systems can be massively parallel (super) computers, 2D/3D many-core systems, cloud computing approaches, or intelligent combinations of such technologies. Topics of interest include, but are not limited to: new software architectures for massively parallel systems, software solutions to cope with hardware failures, new memory hierarchy architectures, low-power single and multi-core architectures, new interconnect architectures, novel energy efficient system designs, energy efficient programming techniques.

    A2 Communication, Consumer and Multimedia Systems (click to open)

    Chair: Frank Kienle, Technical University of Kaiserslautern, DE, Contact

    Co-Chair:

    Topic Members (click to open)

    • Amer Baghdadi, TELECOM Bretagne, FR, Contact
    • christos-savvas [dot] bouganisatimperial [dot] ac [dot] uk, Contact
    • Fabien Clermidy, CEA-LETI, FR, Contact
    • Ilker Hamzaoglu, Sabanci University, TR, Contact
    • Guido Masera, Politecnico di Torino, IT, Contact
    • steffen [dot] paulatitem [dot] uni-bremen [dot] de, Contact
    • Sergio Saponara, University of Pisa, IT, Contact
    • Ioannis Sourdis, TU Delft, NL, Contact
    • Theo Theocharides, University of Cyprus, CY, Contact

    Practical design experience for communication, multimedia and consumer systems like smartphones, smart-books/tablets; examples are digital integrated circuits design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software defined radio systems; embedded systems design in the field of audio, video and vision domain; Application Specific Processors (ASP)/ Digital Signal Processors (DSP) for these domains.

    A3 Transportation, Management and Energy Generation Systems (click to open)

    Chair: Marco Di natale, Scuola Superiore S. Anna, IT, Contact

    Co-Chair: Davide Brunelli, University of Trento, IT, Contact

    Topic Members (click to open)

    • Juergen Becker, KIT - Karlsruher Institut für Technolgie, DE, Contact
    • Joachim Gerlach, Albstadt-Sigmaringen University, DE, Contact
    • Riccardo Mariani, YOGITECH SpA, IT, Contact
    • Geoff Merrett, University of Southampton, UK, Contact
    • aniatcs [dot] ucla [dot] edu, Contact
    • e [dot] popoviciatucc [dot] ie, Contact
    • vratpurdue [dot] edu, Contact
    • Martino Ruggiero, EPFL, CH, Contact
    • Christian Sebeke, Robert Bosch GmbH, DE, Contact
    • Haibo Zeng, General Motors, US, Contact

    Practical design experiences for transportation and energy generation and distribution systems and applications: analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures and integrated sensors and transducers, RF architectures, networks of systems, energy scavenging and harvesting methods from environmental sources. Practical applications of design methods to transportation and energy systems, including models, methods and tools, design of hardware and software components, architecture analysis and optimization, component-oriented design and system-level analysis and validation. Hardware and software solutions to address energy management: components of different nature with focus on energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems and optimization of system energy efficiency.

    A4 Medical and Healthcare Systems (click to open)

    Chair: chris [dot] vanhoofatimec [dot] be, Contact

    Co-Chair: Yihui Chen, Bio Engineering Laboratory (BEL), ETH Zurich, CH, Contact

    Topic Members (click to open)

    • alexandre [dot] schmidatepfl [dot] ch, Contact
    • Roland Thewes, TU Berlin, DE, Contact

    Medical, healthcare, and life science applications require increasingly smarter and smaller devices and personalized medicine will lead to a significant increase in both complex lab solutions as well as a myriad of consumer-like disposable devices. Application examples such as multi-physics nano-bio transducers, cellular interfacing chips, multi-parameter biosensors, pharmaceutical assay chips, implantable and wearable wireless devices for patient monitoring and therapy will reveal complex heterogeneous microsystem designs and design methods, multi-level modeling approaches, co-development of design and process technology.

    A5 Secure Systems (click to open)

    Chair: Jérôme Quévremont, Thales, FR, Contact

    Co-Chair: Patrick Schaumont, Virginia Tech, US, Contact

    Topic Members (click to open)

    • guido [dot] bertoniatst [dot] com, Contact
    • Laurent Fesquet, TIMA - Grenoble Institute of Technology, FR, Contact
    • Maire O'Neill, Queen's University Belfast, UK, Contact
    • Francesco Regazzoni, Université catholique de Louvain and ALaRI, CH, Contact
    • Lionel TORRES, LIRMM - University Montpellier 2, FR, Contact
    • ingrid [dot] verbauwhedeatesat [dot] kuleuven [dot] be, Contact

    Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

    A6 Reliable and Reconfigurable Systems (click to open)

    Chair: jayalaatucm [dot] es, Contact

    Co-Chair: santambratmit [dot] edu, Contact

    Topic Members (click to open)

    • Juergen Becker, KIT - Karlsruher Institut für Technolgie, DE, Contact
    • Andrea Calimera, Politecnico di Torino, IT, Contact
    • Jose M. Moya, Universidad Politecnica de Madrid, ES, Contact
    • vincenzo [dot] ranaatepfl [dot] ch, Contact

    This topic covers the area of reliable and adaptive systems for practical applications. The scope of this topic includes, but not limited to, the development, optimization and practical application mechanisms to compensate for aging and temperature, development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

    A7 Industrial Experiences Brief Papers (click to open)

    Chair: Enrico Macii, Politecnico di Torino, IT, Contact

    Co-Chair: Ahmed Jerraya, CEA Leti, FR, Contact

    Topic Members (click to open)

    • Roberto Zafalon, STMicroelectronics, IT, Contact

    Short or brief papers with a limit of two pages are solicited that relate to industrial research and practice: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanism. Product presentations and announcements are strongly discouraged and will not be considered for publication.


    Track T: Test Methods and Tools (click to open)

    addressing design-oriented embedded test solutions as well as defect analysis, modeling, test generation and silicon debugging. Emphasis is on both system- and chip-level test.

    Track Chair: Erik Jan Marinissen, IMEC, BE, Contact

    Topics

    T1 Test for Defects, Variability, and Reliability (click to open)

    Chair: Sandip Kundu, University of Massachusetts, US, Contact

    Co-Chair: Bram Kruseman, NXP Semiconductors, NL, Contact

    Topic Members (click to open)

    • Robert Aitken, ARM, US, Contact
    • kjleeatmail [dot] ncku [dot] edu [dot] tw, Contact
    • , Contact
    • Markus Rudack, Intel Mobile Communications GmbH, DE, Contact
    • jaume [dot] seguraatuib [dot] es, Contact
    • Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact

    Identification, characterization and modeling of defects, faults and degradation mechanisms; Defect based fault analysis, Simulation and ATPG of defect based faults; Reliability analysis and modeling techniques, FMEA and Physics of failure; Test for noise and uncertainty; Design for Reliability and Design for Variability and their impact on test; Test and reliability of redundant systems; Test and reliability issues in the presence of leakage; Challenges of ultra low-power design on test and reliability; Modeling and test techniques for physical sources of errors such as process, voltage and temperature variations; Error-resilient nano design systems.

    T2 Test Generation, Simulation and Diagnosis (click to open)

    Chair: Nicola Nicolici, McMaster University, CA, Contact

    Co-Chair: Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact

    Topic Members (click to open)

    • Bernd Becker, University of Freiburg, DE, Contact
    • Seiji Kajihara, Kyushu Institute of Technology, JP, Contact
    • frank [dot] poehlatintel [dot] com, Contact
    • matteo sonza reorda, politecnico di torino - DAUIN, IT, Contact
    • Arnau Virazel, LIRMM / Univ. Montpellier, FR, Contact

    Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs.

    T3 Test for Mixed-Signal, Analog, RF, MEMS (click to open)

    Chair: Hans Kerkhoff, University of Twente / CTIT, NL, Contact

    Co-Chair: Tracy021 Tracy021, 123, BH, Contact

    Topic Members (click to open)

    • azaisatlirmm [dot] fr, Contact
    • Sebastian Sattler, University Erlangen-Nuermberg, DE, Contact
    • haralampos [dot] stratigopoulosatlip6 [dot] fr, Contact

    Test techniques for mixed-signal, RF and multi-GHz electronics; test techniques for embedded MEMS/bioMEMS/MOEMS sensors and actuators; assembly engineering for SiP/SoC/SoP/PoP; Failure modeling and analysis techniques; defect characterization and fault modeling; fault simulation and test generation algorithms; DfT/DfM/DfY/DfR (DfX) techniques; BIST; test coverage metrics and statistical modeling; effective defect screening techniques; diagnosis and self-repair.

    T4 Test Access, Design-for-Test, Test Compression, System Test (click to open)

    Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

    Co-Chair: rkapuratsynopsys [dot] com, Contact

    Topic Members (click to open)

    • davide [dot] appelloatst [dot] com, Contact
    • Luigi DILILLO, LIRMM, FR, Contact
    • marie-lise [dot] flottesatlirmm [dot] fr, Contact
    • Paolo PRINETTO, Politecnico di Torino, IT, Contact
    • Nur Touba, University of Texas at Austin, US, Contact
    • Jerzy Tyszer, Poznan University of Technology, PL, Contact
    • Bart Vermeulen, NXP Semiconductors, NL, Contact
    • Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact

    Design for test, debug and manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DfT techniques, DfT for secure systems, Dft economics. Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; testing 3D (TSV-based) chips; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor based test; infrastructure IP; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies.

    T5 On-Line Testing and Fault Tolerance (click to open)

    Chair: Cecilia Metra, University of Bologna, IT, Contact

    Co-Chair: Lorena Anghel, TIMA, FR, Contact

    Topic Members (click to open)

    • Jaume Abella, Barcelona Supercomputing Center, ES, Contact
    • cristiana [dot] bolchiniatpolimi [dot] it, Contact
    • Dimitris Gizopoulos, University of Athens, Department of Informatics & Telecommunications, GR, Contact
    • Maxime Bizance, Metronome, FR, Contact
    • Diana Marculescu, Carnegie Mellon University, US, Contact
    • reza basirirad, rayan co., FR, Contact
    • ilia [dot] polianatuni-passau [dot] de, Contact
    • Xavier Vera, Intel, ES, Contact

    Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependability evaluation, dependable system design; redundant systems design; hardware/software recovery; self-repair; fault tolerance; on-line testing and fault tolerance for industrial applications.


    Track E: Embedded Systems Software (click to open)

    is devoted to modeling, analysis, design and deployment of Embedded Software. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on embedded software platforms, software integration, adaptive real-time systems, and dependable systems.

    Track Chair: Petru Eles, University of Linkoeping, SE, Contact

    Topics

    E1 Real-time, Networked and Dependable Systems (click to open)

    Chair: lipariatsssup [dot] it, Contact

    Co-Chair: Peter Puschner, Vienna University of Technology, AT, Contact

    Topic Members (click to open)

    • Gregor Gössler, INRIA, FR, Contact
    • r [dot] kirneratherts [dot] ac [dot] uk, Contact
    • iamcgleeatgmail [dot] com, Contact
    • liuatcse [dot] tamu [dot] edu, Contact
    • Xue Liu, McGill University, CA, Contact
    • Stefan M. Petters, CISTER-ISEP, IPP, PT, Contact
    • Binoy Ravindran, Virginia Tech, US, Contact
    • stavrosateecs [dot] berkeley [dot] edu, Contact

    Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; tools and design methods for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications;

    E2 Compilers and Software Synthesis for Embedded Systems (click to open)

    Chair: bfrankeatinf [dot] ed [dot] ac [dot] uk, Contact

    Co-Chair: Heiko Falk, Ulm University, DE, Contact

    Topic Members (click to open)

    • Alain [dot] Darteatens-lyon [dot] fr, Contact
    • Frank Hannig, University of Erlangen-Nuremberg, DE, Contact
    • Florence Maraninchi, Grenoble INP / Ensimag & VERIMAG, FR, Contact
    • Rodric Rabbah, IBM Research, US, Contact

    Software synthesis; compilers; code generation; dynamic compilation for embedded systems; software generation tool chain; software environment and generation for design space exploration (compilers, simulators, synthesis tools); retargetable compilers for MPSOC and reconfigurable platforms; compilers for embedded multi-core systems; compiler and software synthesis for low power

    E3 Model-Based Design and Verification for Embedded Systems (click to open)

    Chair: Wang Yi, Uppsala University, SE, Contact

    Co-Chair: Saddek Bensalem, Université Joseph Fourier, FR, Contact

    Topic Members (click to open)

    • bertrand [dot] jeannetatinrialpes [dot] fr, Contact
    • Axel Legay, INRIA and Aalborg, FR, Contact
    • marc [dot] pouzetatens [dot] fr, Contact
    • Roychoudhury Abhik, National University of Singapore, SG, Contact
    • Natasha Sharygina, USI, CH, Contact
    • sokolskyatcis [dot] upenn [dot] edu, Contact
    • veithatforsyte [dot] tuwien [dot] ac [dot] at, Contact

    Model-based methods for embedded system design; verification of embedded systems; model-based software architectures; model-based design for control applications; model-based software testing, software/system integration and deployment; tools for model-based embedded system design; software verification;

    E4 Embedded Software Architectures (click to open)

    Chair: Gabriela Nicolescu, Ecole Polytechnique de Montreal, CA, Contact

    Co-Chair: Oliver Bringmann, FZI, DE, Contact

    Topic Members (click to open)

    • Gero Dittmann, IBM, DE, Contact
    • Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
    • huy-nam [dot] nguyenatbull [dot] net, Contact
    • Alex Orailoglu, UC San Diego, US, Contact
    • Frank Slomka, Ulm University, DE, Contact

    Software architectures for MPSoC, multi/many-core and GPU-based systems; programming languages for embedded MPSoC, multi/many-core and GPU-based systems; virtualization for embedded systems, including safety and security aspects; resources constrained middleware and Run-Time Environment (RTE) architectures; software support for reconfigurable components and accelerators; software architectures for low power and low temperature;

    E5 Cyber-Physical Systems (click to open)

    Chair: Samarjit Chakraborty, TU Munich, DE, Contact

    Co-Chair: Kan Qian, TU/e, NL, Contact

    Topic Members (click to open)

    • zaheratillinois [dot] edu, Contact
    • Anuradha Annaswamy, MIT, US, Contact
    • Rolf Ernst, TU Braunschweig, DE, Contact
    • palopoliatdisi [dot] unitn [dot] it, Contact
    • Subodh Gupte, Open-silicon, IN, Contact

    High-level design, optimization and analysis of networked control and switched control systems; control/architecture co-design for distributed embedded systems; formal semantics, verification, model checking and abstraction refinement techniques for control software and systems; simulation and testing; architectures; modeling techniques; architecture-aware controller synthesis; model-based approaches to cyber-physical systems design; reliability-aware design and fault-tolerance; certification issues; specification languages and programming support; case studies in cyber-physical systems such as from automotive systems and avionics, smart buildings and smart grids;