Date: Tuesday 13 March 2012
Time: 10:30 - 12:30
Location / Room: Booth 50, Exhibition

Organisers:
J Lienig, TU Dresden,
A Vörg, edacentrum,

Moderator:
R Fischbach, TU Dresden,

Time	Label	Presentation Title Authors
07:17		GSNOC - A GENERIC SCALABLE SIMULATION FRAMEWORK FOR 3-DIMENSION NETWORKS-ON-CHIP Authors: Haoyuan Ying1, Ashok Jaiswal1, Philip Gottschling1, Thomas Hollstein2 and Klaus Hofmann1 1Darmstadt TU, Germany; 2Tallinn TU, Estonia Abstract
07:17		MARCIATESTA++: AN AUTOMATIC GENERATOR OF ASSEMBLY TEST PROGRAMS FOR MICROPROCESSORS' DATA AND INSTRUCTION CACHES. Authors: Giulio Gambardella, Daniele Rolfo, Marco Indaco, Stefano Di Carlo and Paolo Prinetto, Politecnico di Torino, Italy Abstract
07:17		ADAGE: ADAPTIVE ECC AUTOMATIC GENERATOR Authors: Marco INDACO, Michele Fabiano, Roberto Piazza, Stefano Di Carlo and Paolo Prinetto, Politecnico di Torino, Italy Abstract
07:17		A TOOL FOR MODELING AND ANALYSIS OF ANALOG CIRCUITS Authors: Henda Aridhi1, Sofiene Tahar2, Mohamed Zaki2 and Ons Lahiouel2 1Concordia U, Canada; 2Concordia University, Canada Abstract
07:17		C++TESK TESTING TOOLKIT Authors: Mikhail Chupilko and Alexander Kamkin, Institute for System Programming of RAS, Russian Federation Abstract
07:17		C-BASED TIMING DRIVEN DESIGN - C-BASED TIMING DRIVEN HIGH-LEVEL DESIGN SYSTEM FOR SYSTEM LSI Authors: Takashi Kambe1 and Shuji Tsukiyama2 1Kinki University, Japan; 2Chuo University, Japan Abstract
07:17		IEEE P1687 IJTAG DEMONSTRATOR ON FPGA Authors: Konstantin Shibin1, Sergei Devadze2, Artur Jutman2 and Igor Aleksejev1 1Tallinn TU, Estonia; 2Testonica Lab, Estonia Abstract
07:17		RIVER ARCHITECTURE - RIVER: RECONFIGURABLE PRE-SYNTHESIZED-STREAMING ARCHITECTURE FOR SIGNAL PROCESSING ON FPGAS Authors: Dominic Hillenbrand, Christian Brugger and Matthias Balzer, KIT - Karlsruhe Institute of Technology, Germany Abstract
12:30		End of session