2.8 Beyond CMOS - Benchmarking for Future Technologies

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Date: Thursday, January 24, 2019
Time: 07:56 - 07:56
Location / Room:

Organiser:
R Popp, edacentrum, , Contact Ralf Popp

Moderators:
C M Sotomayor Torres, Catalan Institute of Nanotechnology, , Contact
W Rosenstiel, Tuebingen University and edacentrum, , Contact Wolfgang Rosenstiel

Of key importance is to address the technological challenges posed by the emerging nanoelectronic concepts, of which a selection will be presented within the tutorial. After an overview on emerging technologies and their design aspects the embedded tutorial will present first benchmarking results for beyond CMOS technologies. Parameters to be considered include gain, signal/noise ration, non-linearity, speed, power consumption, architecture and integrability, efficiency, tolerances and manufacturability as well as the timeline of each potential technology.

TimeLabelPresentation Title
Authors
07:56EMERGING TECHNOLOGIES: MORE MOORE AND MORE THAN MOORE
Author:
Mart Graef, Delft TU,
Abstract
07:56TECHNOLOGY AND DESIGN CHALLENGES IN FUTURE LOW POWER MEMORY DEVICES AND CIRCUITS
Author:
Paolo Fantini, Micron Semiconductors,
Abstract
07:56BRIDGING TECHNOLOGY AND DESIGN FOR BEYOND CMOS
Author:
Paolo Lugli, Munich TU,
Abstract
07:56BRIDGING TECHNOLOGY AND DESIGN IN MORE THAN MOORE
Author:
Adrian Ionescu, EPF Lausanne,
Abstract
07:56BENCHMARKING FOR BEYOND CMOS TECHNOLOGIES
Author:
Jouni Ahopelto, VTT,
Abstract
07:56End of session