DATE 2012 Proceedings - Author Index

Printer-friendly versionPDF version

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]


A

Aasaraai, K
Abstract Icon PDF Icon Toward Virtualizing Branch Direction Prediction [p. 455]
Abate, F
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Abdallah, L
Abstract Icon PDF Icon Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Abed, I S
Abstract Icon PDF Icon Double-Patterning Friendly Grid-Based Detailed Routing with Online Conflict Resolution [p. 1475]
Abelein, U
Abstract Icon PDF Icon Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Abellan, J L
Abstract Icon PDF Icon Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Aboushady, H
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Abraham, J A
Abstract Icon PDF Icon On-Chip Source Synchronous Interface Timing Test Scheme with Calibration [p. 1146]
Acacio, M E
Abstract Icon PDF Icon Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Acquaviva, A
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Adlkofer, H
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Adve, S V
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Afzali-Kusha, A
Abstract Icon PDF Icon An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Ahn, J H
Abstract Icon PDF Icon CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Ahopelto, J
Abstract Icon PDF Icon Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Aisopos, K
Abstract Icon PDF Icon PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Akbari, S
Abstract Icon PDF Icon AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Akesson, B
Abstract Icon PDF Icon DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]
Abstract Icon PDF Icon Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Aksanli, B
Abstract Icon PDF Icon Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers [p. 175]
Aksoy, L
Abstract Icon PDF Icon Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Aktouf, O-E-K
Abstract Icon PDF Icon Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Al-Faruque, M A
Abstract Icon PDF Icon Intelligent and Collaborative Embedded Computing in Automation Engineering [p. 344]
Abstract Icon PDF Icon Towards Parallel Execution of IEC 61131 Industrial Cyber-Physical Systems Applications [p. 554]
Al-Hashimi, B M
Abstract Icon PDF Icon Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Almeroth, B
Abstract Icon PDF Icon Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Aloufi, M
Abstract Icon PDF Icon Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Altet, J
Abstract Icon PDF Icon Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Alvarez-Herault, J
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Amara, A
Abstract Icon PDF Icon Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Ambrose, A
Abstract Icon PDF Icon A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Anagnostopoulos, I
Abstract Icon PDF Icon A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Anderson, J
Abstract Icon PDF Icon Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Anghel, L
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Anis, M
Abstract Icon PDF Icon AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Annaswamy, A
Abstract Icon PDF Icon Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Appleton, E
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Aridhi, H
Abstract Icon PDF Icon Towards Improving Simulation of Analog Circuits Using Model Order Reduction [p. 1337]
Ascheid, G
Abstract Icon PDF Icon Hybrid Simulation for Extensible Processor Cores [p. 288]
Ashouei, M
Abstract Icon PDF Icon Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Atienza, D
Abstract Icon PDF Icon Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation [p. 599]
Abstract Icon PDF Icon Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Abstract Icon PDF Icon A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Aubert, A
Abstract Icon PDF Icon Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Augustine, C
Abstract Icon PDF Icon A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach [p. 1443]
Austin, T
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Avresky, D
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Axer, P
Abstract Icon PDF Icon Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Ayoub, R
Abstract Icon PDF Icon TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs [p. 593]
Azevedo, J
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]

B

Babayan, E
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Bahl, S
Abstract Icon PDF Icon EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Bainbridge, W J
Abstract Icon PDF Icon Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Bamakhrama, M A
Abstract Icon PDF Icon A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Banerjee, A
Abstract Icon PDF Icon Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]
Abstract Icon PDF Icon Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Baronti, F
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Bartolini, A
Abstract Icon PDF Icon Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]
Bartzas, A
Abstract Icon PDF Icon A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Basten, T
Abstract Icon PDF Icon Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]
Abstract Icon PDF Icon Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Basu, S
Abstract Icon PDF Icon Correct-by-Construction Multi-Component SoC Design [p. 647]
Bathen, L A D
Abstract Icon PDF Icon VaMV: Variability-aware Memory Virtualization [p. 284]
Abstract Icon PDF Icon 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]
Battezzati, N
Abstract Icon PDF Icon SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Bauer, L
Abstract Icon PDF Icon Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]
Abstract Icon PDF Icon Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Baumanns, S
Abstract Icon PDF Icon Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Beaumont, M
Abstract Icon PDF Icon SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Becker, B
Abstract Icon PDF Icon On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]
Abstract Icon PDF Icon Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Becker, J
Abstract Icon PDF Icon A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]
Abstract Icon PDF Icon On Demand Dependent Deactivation of Automotive ECUs [p. 69]
Abstract Icon PDF Icon Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Becker, M
Abstract Icon PDF Icon MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Belta, C
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Benini, L
Abstract Icon PDF Icon Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Abstract Icon PDF Icon Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]
Abstract Icon PDF Icon Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]
Abstract Icon PDF Icon Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Abstract Icon PDF Icon A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]
Abstract Icon PDF Icon P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Abstract Icon PDF Icon Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]
Abstract Icon PDF Icon An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Benkner, S
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Benoit, P
Abstract Icon PDF Icon Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
Berangi, R
Abstract Icon PDF Icon AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Berkelaar, M
Abstract Icon PDF Icon Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Beroulle, V
Abstract Icon PDF Icon Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Bertacco, V
Abstract Icon PDF Icon Approximating Checkers for Simulation Acceleration [p. 153]
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Bertels, K
Abstract Icon PDF Icon Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Bertozzi, D
Abstract Icon PDF Icon Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Abstract Icon PDF Icon A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Bertrand, D
Abstract Icon PDF Icon Challenges and New Trends in Probabilistic Timing Analysis [p. 810]
Beste, M
Abstract Icon PDF Icon Layout-Driven Robustness Analysis for Misaligned Carbon Nanotubes in CNTFET-based Standard Cells [p. 1609]
Bhardwaj, K
Abstract Icon PDF Icon An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Bhatia, S
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Bi, X
Abstract Icon PDF Icon Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Bittner, K
Abstract Icon PDF Icon Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Blech, J O
Abstract Icon PDF Icon Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Blom, H
Abstract Icon PDF Icon Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Bocca, A
Abstract Icon PDF Icon Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Bolchini, C
Abstract Icon PDF Icon An Adaptive Approach for Online Fault Management in Many-Core Architectures [p. 1429]
Bombieri, N
Abstract Icon PDF Icon FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]
Bonamy, R
Abstract Icon PDF Icon UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Bonilla, E
Abstract Icon PDF Icon Predicting Best Design Trade-offs: A Case Study in Processor Customization [p. 1030]
Borde, E
Abstract Icon PDF Icon Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Bordoloi, U D
Abstract Icon PDF Icon A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Bortolotti, D
Abstract Icon PDF Icon Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Bose, P
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Bosio, A
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Bovington, J
Abstract Icon PDF Icon Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Bowman, K
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Bozga, M
Abstract Icon PDF Icon State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Brachtendorf, H G
Abstract Icon PDF Icon Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Brandl, M
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Brault, J -M
Abstract Icon PDF Icon NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Brayton, R
Abstract Icon PDF Icon Mapping into LUT Structures [p. 1579]
Brayton, R K
Abstract Icon PDF Icon Scalable Progress Verification in Credit-Based Flow-Control Systems [p. 905]
Brenner, U
Abstract Icon PDF Icon VLSI Legalization with Minimum Perturbation by Iterative Augmentation [p. 1385]
Bringmann, O
Abstract Icon PDF Icon Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Abstract Icon PDF Icon Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies [p. 862]
Brisk, P
Abstract Icon PDF Icon Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Brockman, J B.
Abstract Icon PDF Icon CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Brokalakis, A
Abstract Icon PDF Icon An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Bruening, A
Abstract Icon PDF Icon Memristor Technology in Future Electronic System Design [p. 592]
Abstract Icon PDF Icon Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Brunelli, D
Abstract Icon PDF Icon Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Buckl, C
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Abstract Icon PDF Icon Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Burg, A
Abstract Icon PDF Icon Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Burgio, P
Abstract Icon PDF Icon Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]
Buyuktosunoglu, A
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]

C

Cai, Y
Abstract Icon PDF Icon Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Calazans, N
Abstract Icon PDF Icon An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design [p. 224]
Calimera, A
Abstract Icon PDF Icon IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Campagna, S
Abstract Icon PDF Icon An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation [p. 1433]
Campbell, S A
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Camposano, R
Abstract Icon PDF Icon Moore Meets Maxwell [p. 1275]
Canedo, A
Abstract Icon PDF Icon Intelligent and Collaborative Embedded Computing in Automation Engineering [p. 344]
Abstract Icon PDF Icon Towards Parallel Execution of IEC 61131 Industrial Cyber-Physical Systems Applications [p. 554]
Carloni, L P
Abstract Icon PDF Icon Compositional System-Level Design Exploration with Planning of High-Level Synthesis [p. 641]
Carr, S B
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Catthoor, F
Abstract Icon PDF Icon Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Abstract Icon PDF Icon A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Cenni, F
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Cha, B
Abstract Icon PDF Icon Salvaging Chips with Caches beyond Repair [p. 1263]
Chakrabarty, K
Abstract Icon PDF Icon Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Abstract Icon PDF Icon Test Pin Count Reduction for NoC-based Test Delivery in Multicore SOCs [p. 787]
Abstract Icon PDF Icon A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Chakraborty, K
Abstract Icon PDF Icon An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Chakraborty, S
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Abstract Icon PDF Icon Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Abstract Icon PDF Icon Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Chandrasekar, K
Abstract Icon PDF Icon A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Chang, K-H
Abstract Icon PDF Icon RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Chang, L-P
Abstract Icon PDF Icon Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks [p. 117]
Chang, N
Abstract Icon PDF Icon Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Abstract Icon PDF Icon State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Chang, S-C
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chang, Y-W
Abstract Icon PDF Icon Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]
Chao, H-L
Abstract Icon PDF Icon Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chatterjee, D
Abstract Icon PDF Icon Approximating Checkers for Simulation Acceleration [p. 153]
Chaturvedi, S
Abstract Icon PDF Icon Static Analysis of Asynchronous Clock Domain Crossings [p. 1122]
Chatziparaskevas, G
Abstract Icon PDF Icon An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Chen, C
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Abstract Icon PDF Icon Mapping into LUT Structures [p. 1579]
Chen, C-L
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Chen, D
Abstract Icon PDF Icon Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Chen, H
Abstract Icon PDF Icon QBF-Based Boolean Function Bi-Decomposition [p. 816]
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Chen, H-M
Abstract Icon PDF Icon Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization [p. 1391]
Abstract Icon PDF Icon On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, J
Abstract Icon PDF Icon A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Chen, J-J
Abstract Icon PDF Icon Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Chen, K
Abstract Icon PDF Icon CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Chen, L
Abstract Icon PDF Icon Online Scheduling for Multi-Core Shared Reconfigurable Fabric [p. 582]
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Chen, M-L
Abstract Icon PDF Icon On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, Q
Abstract Icon PDF Icon Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]
Abstract Icon PDF Icon Characterization of the Bistable Ring PUF [p. 1459]
Chen, S-H
Abstract Icon PDF Icon On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, S-J
Abstract Icon PDF Icon Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chen, W
Abstract Icon PDF Icon Out-of-Order Parallel Simulation for ESL Design [p. 141]
Chen, Y
Abstract Icon PDF Icon 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]
Abstract Icon PDF Icon Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Abstract Icon PDF Icon Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Abstract Icon PDF Icon Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Chen, Y-C
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chen, Y-R
Abstract Icon PDF Icon Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chen, Y-T
Abstract Icon PDF Icon Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Cheng, K-T
Abstract Icon PDF Icon Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Cheng, X
Abstract Icon PDF Icon Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Cherkaoui, A
Abstract Icon PDF Icon Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Chian, M
Abstract Icon PDF Icon New Foundry Models - Accelerations in Transformations of the Semiconductor Industry [p. 2]
Chiang, M-F
Abstract Icon PDF Icon A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Chillet, D
Abstract Icon PDF Icon UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Choi, K
Abstract Icon PDF Icon State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Chong, S
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Chou, C-N
Abstract Icon PDF Icon Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Chou, H-M
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chou, H-Z
Abstract Icon PDF Icon RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Choudhary, A
Abstract Icon PDF Icon Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Chua, L O
Abstract Icon PDF Icon Memristor Technology in Future Electronic System Design [p. 592]
Chuang, Y-L
Abstract Icon PDF Icon Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]
Cifrain, M
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Clavier, L
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Colazzo, S
Abstract Icon PDF Icon SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Condo, C
Abstract Icon PDF Icon A Network-on-Chip-based Turbo/LDPC Decoder Architecture [p. 1525]
Cong, J
Abstract Icon PDF Icon Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Abstract Icon PDF Icon Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Constantin, J
Abstract Icon PDF Icon Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Cordes, D
Abstract Icon PDF Icon Multi-Objective Aware Extraction of Task-Level Parallelism Using Genetic Algorithms [p. 394]
Corporaal, H
Abstract Icon PDF Icon Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]
Abstract Icon PDF Icon Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Abstract Icon PDF Icon Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Cosemans, S
Abstract Icon PDF Icon Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Coskun, A K
Abstract Icon PDF Icon Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]
Abstract Icon PDF Icon Analysis and Runtime Management of 3D Systems with Stacked DRAM for Boosting Energy Efficiency [p. 611]
Abstract Icon PDF Icon Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads [p. 994]
Costa, E
Abstract Icon PDF Icon Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Craninckx, J
Abstract Icon PDF Icon Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Cristal, A
Abstract Icon PDF Icon TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Csaba, G
Abstract Icon PDF Icon Characterization of the Bistable Ring PUF [p. 1459]
Cucuccio, A
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Cui, T
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Cui, X
Abstract Icon PDF Icon Modeling and Testing of Interference Faults in the Nano NAND Flash Memory [p. 527]
Cui, Z
Abstract Icon PDF Icon Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Cullmann, C
Abstract Icon PDF Icon Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Cupaiuolo, T
Abstract Icon PDF Icon A Flexible and Fast Software Implementation of the FFT on the BPE Platform [p. 1467]
Czutro, A
Abstract Icon PDF Icon On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]

D

Daghar, A
Abstract Icon PDF Icon Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Damavandpeyma, M
Abstract Icon PDF Icon Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Daneshtalab, M
Abstract Icon PDF Icon CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Dang, X
Abstract Icon PDF Icon S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Danger, J-L
Abstract Icon PDF Icon RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Daniel, L
Abstract Icon PDF Icon An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems [p. 1203]
Darringer, J A
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Das, A
Abstract Icon PDF Icon Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Abstract Icon PDF Icon PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Das, S
Abstract Icon PDF Icon PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations [p. 550]
Dasgupta, P
Abstract Icon PDF Icon Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]
Dastgeer, U
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
David, A
Abstract Icon PDF Icon State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Davoodi, A
Abstract Icon PDF Icon A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection [p. 1331]
Abstract Icon PDF Icon Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations [p. 1591]
De Jonghe, D
Abstract Icon PDF Icon Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]
Abstract Icon PDF Icon Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
De Micheli, G
Abstract Icon PDF Icon Voltage Propagation Method for 3-D Power Grid Analysis [p. 844]
De Smedt, B
Abstract Icon PDF Icon Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
De, V
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Defo, G B G
Abstract Icon PDF Icon MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Dehaene, W
Abstract Icon PDF Icon Design of a Low-Energy Data Processing Architecture for WSN Nodes [p. 570]
Abstract Icon PDF Icon Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Deniz, E
Abstract Icon PDF Icon Verification Coverage of Embedded Multicore Applications [p. 252]
Densmore, D
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Desbarbieux, J-I
Abstract Icon PDF Icon An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Dey, O
Abstract Icon PDF Icon Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Di Carlo, S
Abstract Icon PDF Icon A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Di Guglielmo, G
Abstract Icon PDF Icon Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Di Guglielmo, L
Abstract Icon PDF Icon Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Di Natale, M
Abstract Icon PDF Icon Task Implementation of Synchronous Finite State Machines [p. 206]
Dilillo, L
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Dimitrakopoulos, G
Abstract Icon PDF Icon Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches [p. 542]
Doemer, R
Abstract Icon PDF Icon Out-of-Order Parallel Simulation for ESL Design [p. 141]
Dogan, A Y
Abstract Icon PDF Icon Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Dolinsky, U
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Domic, A
Abstract Icon PDF Icon Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Donno, M
Abstract Icon PDF Icon Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
dos Santos, L C V
Abstract Icon PDF Icon On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Dousti, M J
Abstract Icon PDF Icon Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric [p. 840]
Drach, N
Abstract Icon PDF Icon An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Drechsler, R
Abstract Icon PDF Icon A Guiding Coverage Metric for Formal Verification [p. 617]
Abstract Icon PDF Icon Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]
Abstract Icon PDF Icon Debugging of Inconsistent UML/OCL Models [p. 1078]
Abstract Icon PDF Icon Eliminating Invariants in UML/OCL Models [p. 1142]
Druml, N
Abstract Icon PDF Icon Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Du, K
Abstract Icon PDF Icon High Performance Reliable Variable Latency Carry Select Addition [p. 1257]
Duan, G
Abstract Icon PDF Icon Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Dutt, N D
Abstract Icon PDF Icon VaMV: Variability-aware Memory Virtualization [p. 284]
Abstract Icon PDF Icon 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]

E

Ebeid, E
Abstract Icon PDF Icon Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Ebrahimi, M
Abstract Icon PDF Icon CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Abstract Icon PDF Icon SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Edwards, D
Abstract Icon PDF Icon Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Een, N
Abstract Icon PDF Icon Mapping into LUT Structures [p. 1579]
Ejlali, A
Abstract Icon PDF Icon SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Eklow, B
Abstract Icon PDF Icon On Effective TSV Repair for 3D-Stacked ICs [p. 793]
Eles, P
Abstract Icon PDF Icon Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]
Abstract Icon PDF Icon A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Ellen, C
Abstract Icon PDF Icon Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Enescu, F
Abstract Icon PDF Icon Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]
Ernst, R
Abstract Icon PDF Icon Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]
Abstract Icon PDF Icon A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]
Abstract Icon PDF Icon Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]
Abstract Icon PDF Icon Optimizing Performance Analysis for Synchronous Dataflow Graphs with Shared Resources [p. 635]
Abstract Icon PDF Icon Challenges and New Trends in Probabilistic Timing Analysis [p. 810]
Abstract Icon PDF Icon Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Etzien, C
Abstract Icon PDF Icon Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Eusse, J
Abstract Icon PDF Icon Hybrid Simulation for Extensible Processor Cores [p. 288]

F

Fabiano, M
Abstract Icon PDF Icon A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Fahmy, S
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Fan, M
Abstract Icon PDF Icon Neighbor-Aware Dynamic Thermal Management for Multi-core Platform [p. 187]
Abstract Icon PDF Icon Harmonic Semi-Partitioned Scheduling for Fixed-Priority Real-Time Tasks on Multi-Core Platform [p. 503]
Fan, X
Abstract Icon PDF Icon Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Fantechi, G
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Fanucci, L
Abstract Icon PDF Icon Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Fatemi, H
Abstract Icon PDF Icon Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems [p. 1048]
Fathy, M
Abstract Icon PDF Icon AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Faura, D
Abstract Icon PDF Icon Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Fernandez, J
Abstract Icon PDF Icon Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Ferrari, A
Abstract Icon PDF Icon Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Fesquet, L
Abstract Icon PDF Icon Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Fettweis, G
Abstract Icon PDF Icon Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) [p. 1161]
Abstract Icon PDF Icon Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Figueras, J
Abstract Icon PDF Icon Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation [p. 1343]
Fiorini, P
Abstract Icon PDF Icon Predictive Control of Networked Control Systems over Differentiated Services Lossy Networks [p. 1245]
Firouzi, F
Abstract Icon PDF Icon NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]
Fischer, V
Abstract Icon PDF Icon Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Flamand, E
Abstract Icon PDF Icon P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Flores, P
Abstract Icon PDF Icon Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Fohler, G
Abstract Icon PDF Icon On-line Scheduling of Target Sensitive Periodic Tasks with the Gravitational Task Model [p. 578]
Fradet, P
Abstract Icon PDF Icon SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Franchi, E
Abstract Icon PDF Icon Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]
Fritz, G
Abstract Icon PDF Icon Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Fu, X
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Fuin, D
Abstract Icon PDF Icon P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Fummi, F
Abstract Icon PDF Icon Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Abstract Icon PDF Icon MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Abstract Icon PDF Icon FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]
Abstract Icon PDF Icon Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Furst, J-N
Abstract Icon PDF Icon Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]

G

Gadkari, A
Abstract Icon PDF Icon An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Gall, H
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Gamatie, A
Abstract Icon PDF Icon Design of Streaming Applications on MPSoCs Using Abstract Clocks [p. 763]
Gan, J
Abstract Icon PDF Icon Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Ganguly, R
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Ganta, D
Abstract Icon PDF Icon ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Gao, J
Abstract Icon PDF Icon A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Gao, M
Abstract Icon PDF Icon Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Gao, P
Abstract Icon PDF Icon Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Garcia-Ortiz, A
Abstract Icon PDF Icon Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]
Garside, J
Abstract Icon PDF Icon Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Garudadri, H
Abstract Icon PDF Icon A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Gatti, M
Abstract Icon PDF Icon Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Gebhard, G
Abstract Icon PDF Icon Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Geilen, M
Abstract Icon PDF Icon Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]
Abstract Icon PDF Icon Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Genser, A
Abstract Icon PDF Icon Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Gerdes, M
Abstract Icon PDF Icon Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Ghodrat, M A
Abstract Icon PDF Icon Optimization Intensive Energy Harvesting [p. 272]
Giegerich, M
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Gielen, G
Abstract Icon PDF Icon Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]
Abstract Icon PDF Icon A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems [p. 751]
Abstract Icon PDF Icon Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]
Abstract Icon PDF Icon Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Abstract Icon PDF Icon Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Girard, P
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Girault, A
Abstract Icon PDF Icon SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Giusto, P
Abstract Icon PDF Icon Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]
Givargis, T
Abstract Icon PDF Icon MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups [p. 1417]
Glass, M
Abstract Icon PDF Icon Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Goehringer, D
Abstract Icon PDF Icon Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Goel, M
Abstract Icon PDF Icon A High Performance Split-Radix FFT with Constant Geometry Architecture [p. 1537]
Goel, S K
Abstract Icon PDF Icon EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Gol, E A
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Goldman, R
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Gomony, M D
Abstract Icon PDF Icon DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]
Gong, J
Abstract Icon PDF Icon Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Goossens, K
Abstract Icon PDF Icon DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]
Abstract Icon PDF Icon Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Abstract Icon PDF Icon A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Goossens, S
Abstract Icon PDF Icon Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Gope, D
Abstract Icon PDF Icon Moore Meets Maxwell [p. 1275]
Goswami, D
Abstract Icon PDF Icon Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Goswami, D
Abstract Icon PDF Icon Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Graeb, H
Abstract Icon PDF Icon ITRS 2011 Analog EDA Challenges and Approaches - Invited Paper [p. 1150]
Graef, M W M
Abstract Icon PDF Icon Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Grass, E
Abstract Icon PDF Icon Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Grivet-Talocia, S
Abstract Icon PDF Icon Moore Meets Maxwell [p. 1275]
Grosse, D
Abstract Icon PDF Icon A Guiding Coverage Metric for Formal Verification [p. 617]
Grudnitsky, A
Abstract Icon PDF Icon Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Gruian, F
Abstract Icon PDF Icon Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Guarnieri, V
Abstract Icon PDF Icon FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]
Guderian, F
Abstract Icon PDF Icon Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Guerra, R
Abstract Icon PDF Icon On-line Scheduling of Target Sensitive Periodic Tasks with the Gravitational Task Model [p. 578]
Guilley, S
Abstract Icon PDF Icon RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Guo, X
Abstract Icon PDF Icon ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Gupta, A
Abstract Icon PDF Icon Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]
Gupta, M S
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Gupta, P
Abstract Icon PDF Icon VaMV: Variability-aware Memory Virtualization [p. 284]
Abstract Icon PDF Icon Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Gupta, R K
Abstract Icon PDF Icon Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]
Gupta, S K
Abstract Icon PDF Icon Salvaging Chips with Caches beyond Repair [p. 1263]
Abstract Icon PDF Icon Layout-Aware Optimization of STT MRAMs [p. 1455]

H

Haddock, T
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Haedicke, F
Abstract Icon PDF Icon A Guiding Coverage Metric for Formal Verification [p. 617]
Hahn, D
Abstract Icon PDF Icon Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Haid, J
Abstract Icon PDF Icon Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Hamdioui, S
Abstract Icon PDF Icon DfT Schemes for Resistive Open Defects in RRAMs [p. 799]
Hameed, F
Abstract Icon PDF Icon Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]
Hammami, O
Abstract Icon PDF Icon NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Hamouche, R
Abstract Icon PDF Icon Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design [p. 1421]
Hamouda, A Y
Abstract Icon PDF Icon AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Han, K
Abstract Icon PDF Icon State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Han, X
Abstract Icon PDF Icon Out-of-Order Parallel Simulation for ESL Design [p. 141]
Han, Y
Abstract Icon PDF Icon A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Hanke, M
Abstract Icon PDF Icon Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]
Hankendi, C
Abstract Icon PDF Icon Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads [p. 994]
Hansen, J
Abstract Icon PDF Icon Multi-Token Resource Sharing for Pipelined Asynchronous Systems [p. 1191]
Hansen, R
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Hapke, F
Abstract Icon PDF Icon EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Haratsch, E F
Abstract Icon PDF Icon Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Hardavellas, N
Abstract Icon PDF Icon Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Hari, S K S
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Haron, N Z
Abstract Icon PDF Icon DfT Schemes for Resistive Open Defects in RRAMs [p. 799]
Harrant, M
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Hartmanns, A
Abstract Icon PDF Icon State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Hasholzner, R
Abstract Icon PDF Icon Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Hassoun, S
Abstract Icon PDF Icon Genetic/Bio Design Automation for (Re-)Engineering Biological Systems [p. 242]
Haubelt, C
Abstract Icon PDF Icon Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
He, Y
Abstract Icon PDF Icon Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Healy, M B
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Hedrich, L
Abstract Icon PDF Icon Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Heer, C
Abstract Icon PDF Icon Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Hely, D
Abstract Icon PDF Icon Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Henkel, J
Abstract Icon PDF Icon Accurate Source-Level Simulation of Embedded Software with Respect to Compiler Optimizations [p. 382]
Abstract Icon PDF Icon Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]
Abstract Icon PDF Icon Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Abstract Icon PDF Icon Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Henry, M B
Abstract Icon PDF Icon ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Henschel, O P
Abstract Icon PDF Icon On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Herkersdorf, A
Abstract Icon PDF Icon Virtual Platforms: Breaking New Grounds [p. 685]
Hermanns, H
Abstract Icon PDF Icon State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Heuser, A
Abstract Icon PDF Icon Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models [p. 1179]
Ho, T-Y
Abstract Icon PDF Icon A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Holt, J
Abstract Icon PDF Icon Verification Coverage of Embedded Multicore Applications [p. 252]
Hopkins, B
Abstract Icon PDF Icon SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Howe, R T
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Hsiao, M S
Abstract Icon PDF Icon RAG: An Efficient Reliability Analysis of Logic Circuits on Graphics Processing Units [p. 316]
Abstract Icon PDF Icon A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Hsiung, P-A
Abstract Icon PDF Icon Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Hsu, H-W
Abstract Icon PDF Icon On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Hsuing, H
Abstract Icon PDF Icon Salvaging Chips with Caches beyond Repair [p. 1263]
Hu, Y
Abstract Icon PDF Icon Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Huang, C-Y
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Abstract Icon PDF Icon Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Huang, H
Abstract Icon PDF Icon Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Abstract Icon PDF Icon Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Huang, J
Abstract Icon PDF Icon Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Huang, K
Abstract Icon PDF Icon Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Huang, M
Abstract Icon PDF Icon Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Huang, P-K
Abstract Icon PDF Icon Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Huang, S
Abstract Icon PDF Icon ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Huebner, M
Abstract Icon PDF Icon Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Huisken, J
Abstract Icon PDF Icon Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Hung, C Y
Abstract Icon PDF Icon Challenges in Verifying an Integrated 3D Design [p. 167]
Huss, A
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Huss, S A
Abstract Icon PDF Icon Side Channel Analysis of the SHA-3 Finalists [p. 1012]

I

Ienne, P
Abstract Icon PDF Icon Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Ike, A
Abstract Icon PDF Icon Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Illikkal, R
Abstract Icon PDF Icon PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Indaco, M
Abstract Icon PDF Icon A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Irwin, M J
Abstract Icon PDF Icon An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Iyengar, V
Abstract Icon PDF Icon Challenges in Verifying an Integrated 3D Design [p. 167]
Iyer, R
Abstract Icon PDF Icon PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]

J

Jacobson, H
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Jafari, F
Abstract Icon PDF Icon Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]
Jahn, M
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Jandhyala, V
Abstract Icon PDF Icon Moore Meets Maxwell [p. 1275]
Jang, M-W
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Jang, S
Abstract Icon PDF Icon Mapping into LUT Structures [p. 1579]
Janota, M
Abstract Icon PDF Icon QBF-Based Boolean Function Bi-Decomposition [p. 816]
Janssen, R
Abstract Icon PDF Icon Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Jantsch, A
Abstract Icon PDF Icon Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]
Abstract Icon PDF Icon Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC [p. 1289]
Jedda, H
Abstract Icon PDF Icon Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]
Jentsch, M
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Jeong, K
Abstract Icon PDF Icon MAPG: Memory Access Power Gating [p. 1054]
Jerke, G
Abstract Icon PDF Icon Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Jha, N K
Abstract Icon PDF Icon Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals [p. 437]
Jiang, J
Abstract Icon PDF Icon On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Jiang, K
Abstract Icon PDF Icon Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]
Jiang, L
Abstract Icon PDF Icon On Effective TSV Repair for 3D-Stacked ICs [p. 793]
Abstract Icon PDF Icon Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]
Jin, T
Abstract Icon PDF Icon Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Jin, Y
Abstract Icon PDF Icon Post-Deployment Trust Evaluation in Wireless Cryptographic ICs [p. 965]
Jones, A K
Abstract Icon PDF Icon Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Jones, D L
Abstract Icon PDF Icon Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Jones, S
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Jonsson, F
Abstract Icon PDF Icon A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Jouppi, N P.
Abstract Icon PDF Icon CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Jovic, J
Abstract Icon PDF Icon Hybrid Simulation for Extensible Processor Cores [p. 288]
Juan, D-C
Abstract Icon PDF Icon Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]

K

Kahng, A B
Abstract Icon PDF Icon MAPG: Memory Access Power Gating [p. 1054]
Kakoee, M R
Abstract Icon PDF Icon A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]
Kalla, P
Abstract Icon PDF Icon Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]
Kalligeros, E
Abstract Icon PDF Icon Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches [p. 542]
Kamal, M
Abstract Icon PDF Icon An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Kandemir, M
Abstract Icon PDF Icon Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Kang, S
Abstract Icon PDF Icon MAPG: Memory Access Power Gating [p. 1054]
Karim, K S
Abstract Icon PDF Icon AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Karimi, N
Abstract Icon PDF Icon Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Karlsson, D
Abstract Icon PDF Icon Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Karnik, T
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Karri, R
Abstract Icon PDF Icon Logic Encryption: A Fault Analysis Perspective [p. 953]
Kasper, M
Abstract Icon PDF Icon Side Channel Analysis of the SHA-3 Finalists [p. 1012]
Kathareios, G
Abstract Icon PDF Icon A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Katoen, J-P
Abstract Icon PDF Icon Model Checking of Scenario-Aware Dataflow with CADP [p. 653]
Katz, Y
Abstract Icon PDF Icon Generating Instruction Streams Using Abstract CSP [p. 15]
Kazmierski, T J
Abstract Icon PDF Icon Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Keng, B
Abstract Icon PDF Icon Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Kerkhoff, H G
Abstract Icon PDF Icon Monitoring Active Filters under Automotive Aging Scenarios with Embedded Instrument [p. 1096]
Kessler, C
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Kestur, S
Abstract Icon PDF Icon An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Khatri, S P
Abstract Icon PDF Icon A Fast, Source-Synchronous Ring-based Network-on-Chip Design [p. 1489]
Khellah, M
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Kiamehr, S
Abstract Icon PDF Icon NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]
Kim, D
Abstract Icon PDF Icon A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]
Kim, H
Abstract Icon PDF Icon On-Chip Source Synchronous Interface Timing Test Scheme with Calibration [p. 1146]
Kim, N S
Abstract Icon PDF Icon Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors [p. 1134]
Kim, Y
Abstract Icon PDF Icon Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]
Abstract Icon PDF Icon A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Kirsch, C
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Kluge, F
Abstract Icon PDF Icon Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Knoedler, K
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Knoll, A
Abstract Icon PDF Icon Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Abstract Icon PDF Icon Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
Knoth, C
Abstract Icon PDF Icon Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]
Kocabas, U
Abstract Icon PDF Icon PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Kocik, R
Abstract Icon PDF Icon Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design [p. 1421]
Koenig, R
Abstract Icon PDF Icon A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]
Kogel, T
Abstract Icon PDF Icon Virtual Platforms: Breaking New Grounds [p. 685]
Kondratyev, A
Abstract Icon PDF Icon Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Kotiyal, S
Abstract Icon PDF Icon Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder [p. 721]
Kouters, T
Abstract Icon PDF Icon Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Kress, R
Abstract Icon PDF Icon Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Kriebel, F
Abstract Icon PDF Icon Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Krinke, A
Abstract Icon PDF Icon Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Kristic, M
Abstract Icon PDF Icon Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Krone, S
Abstract Icon PDF Icon Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Kulkarni, J
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Kuntz, S
Abstract Icon PDF Icon Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Kunze, M
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Kural, E
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Kuwamura, S
Abstract Icon PDF Icon Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Kwon, S
Abstract Icon PDF Icon A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]

L

Lafaye, M
Abstract Icon PDF Icon Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Lai, L-C
Abstract Icon PDF Icon Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs [p. 1479]
Lam, T-K
Abstract Icon PDF Icon Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]
Landis, D L
Abstract Icon PDF Icon Hazard Driven Test Generation for SMT Processors [p. 256]
Landolt, F
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Larsen, K G
Abstract Icon PDF Icon State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Lau, J
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Laur, R
Abstract Icon PDF Icon Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Lavagno, L
Abstract Icon PDF Icon Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Laversanne, S
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Le, B
Abstract Icon PDF Icon Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Abstract Icon PDF Icon Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Lee, C L
Abstract Icon PDF Icon Modeling and Testing of Interference Faults in the Nano NAND Flash Memory [p. 527]
Lee, C-J
Abstract Icon PDF Icon Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization [p. 1391]
Lee, D
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Lee, M-C
Abstract Icon PDF Icon Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Lee, S
Abstract Icon PDF Icon A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]
Abstract Icon PDF Icon Bloom Filter-based Dynamic Wear Leveling for Phase-Change RAM [p. 1513]
Lee, W S
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Legay, A
Abstract Icon PDF Icon State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Lehner, W
Abstract Icon PDF Icon Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) [p. 1161]
Leteinturier, P
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Leupers, R
Abstract Icon PDF Icon Hybrid Simulation for Extensible Processor Cores [p. 288]
Abstract Icon PDF Icon Virtual Platforms: Breaking New Grounds [p. 685]
Leveque, A
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Lewis, M
Abstract Icon PDF Icon Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Li, B
Abstract Icon PDF Icon Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Li, H
Abstract Icon PDF Icon Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Abstract Icon PDF Icon Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Abstract Icon PDF Icon A Complexity Adaptive Channel Estimator for Low Power [p. 1531]
Li, H-C
Abstract Icon PDF Icon On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Li, M
Abstract Icon PDF Icon RAG: An Efficient Reliability Analysis of Logic Circuits on Graphics Processing Units [p. 316]
Abstract Icon PDF Icon A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection [p. 1331]
Abstract Icon PDF Icon Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations [p. 1591]
Li, S
Abstract Icon PDF Icon CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Abstract Icon PDF Icon A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Li, T
Abstract Icon PDF Icon Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors [p. 875]
Li, X
Abstract Icon PDF Icon A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Abstract Icon PDF Icon Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Abstract Icon PDF Icon NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Li, Y
Abstract Icon PDF Icon Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Liang, Y
Abstract Icon PDF Icon Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Lilja, D J
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Liljeberg, P
Abstract Icon PDF Icon CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Lin, H-Y
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Lin, R-B
Abstract Icon PDF Icon Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs [p. 1479]
Lin, W-H
Abstract Icon PDF Icon Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks [p. 117]
Lin, X
Abstract Icon PDF Icon State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Lindwer, M
Abstract Icon PDF Icon Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Lippautz, M
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Lisherness, P
Abstract Icon PDF Icon Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Liu, B
Abstract Icon PDF Icon Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Abstract Icon PDF Icon Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Abstract Icon PDF Icon A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems [p. 751]
Abstract Icon PDF Icon Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Liu, C
Abstract Icon PDF Icon Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Liu, D
Abstract Icon PDF Icon A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Liu, G
Abstract Icon PDF Icon Neighbor-Aware Dynamic Thermal Management for Multi-core Platform [p. 187]
Liu, H
Abstract Icon PDF Icon Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Abstract Icon PDF Icon An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]
Liu, H-Y
Abstract Icon PDF Icon Compositional System-Level Design Exploration with Planning of High-Level Synthesis [p. 641]
Liu, S
Abstract Icon PDF Icon Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC [p. 1289]
Liu, S S-Y
Abstract Icon PDF Icon Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization [p. 1391]
Liu, X
Abstract Icon PDF Icon Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Liu, X-X
Abstract Icon PDF Icon Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]
Abstract Icon PDF Icon Parallel Statistical Analysis of Analog Circuits by GPU-accelerated Graph-based Approach [p. 852]
Abstract Icon PDF Icon A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation [p. 1349]
Liu, Y
Abstract Icon PDF Icon A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Lo Iacono, D
Abstract Icon PDF Icon A Flexible and Fast Software Implementation of the FFT on the BPE Platform [p. 1467]
Lochner, H
Abstract Icon PDF Icon Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Loghi, M
Abstract Icon PDF Icon Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Loi, I
Abstract Icon PDF Icon A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]
Abstract Icon PDF Icon An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Lorentz, V
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Louerat, M-M
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Lu, J
Abstract Icon PDF Icon S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Lu, K
Abstract Icon PDF Icon Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level [p. 135]
Lu, S-L
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Lu, Z
Abstract Icon PDF Icon Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]
Abstract Icon PDF Icon Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC [p. 1289]
Lugli, P
Abstract Icon PDF Icon Characterization of the Bistable Ring PUF [p. 1459]
Lukasiewycz, M
Abstract Icon PDF Icon Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Abstract Icon PDF Icon Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Luo, Y
Abstract Icon PDF Icon A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Luy, L
Abstract Icon PDF Icon Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Lv, J
Abstract Icon PDF Icon Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]

M

Macii, A
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Macii, E
Abstract Icon PDF Icon IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Abstract Icon PDF Icon Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Mackay, K
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Madsen, J
Abstract Icon PDF Icon Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Maffione, M
Abstract Icon PDF Icon SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Magno, M
Abstract Icon PDF Icon Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Mahapatra, R N
Abstract Icon PDF Icon A Fast, Source-Synchronous Ring-based Network-on-Chip Design [p. 1489]
Mahmood, H
Abstract Icon PDF Icon Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Mahmood, Z
Abstract Icon PDF Icon An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems [p. 1203]
Mai, K
Abstract Icon PDF Icon Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Majumdar, S
Abstract Icon PDF Icon A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Makosiej, A
Abstract Icon PDF Icon Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Makris, Y
Abstract Icon PDF Icon Post-Deployment Trust Evaluation in Wireless Cryptographic ICs [p. 965]
Maliuk, D
Abstract Icon PDF Icon Post-Deployment Trust Evaluation in Wireless Cryptographic ICs [p. 965]
Mammo, B
Abstract Icon PDF Icon Approximating Checkers for Simulation Acceleration [p. 153]
Mancini, S
Abstract Icon PDF Icon Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow [p. 1130]
Mandal, A
Abstract Icon PDF Icon A Fast, Source-Synchronous Ring-based Network-on-Chip Design [p. 1489]
Mangassarian, H
Abstract Icon PDF Icon Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Marconi, T
Abstract Icon PDF Icon Online Scheduling for Multi-Core Shared Reconfigurable Fabric [p. 582]
Marculescu, D
Abstract Icon PDF Icon Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]
Abstract Icon PDF Icon Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Mariani, G
Abstract Icon PDF Icon Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Maricau, E
Abstract Icon PDF Icon Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]
Abstract Icon PDF Icon Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Marin, P
Abstract Icon PDF Icon Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Marinho, J M
Abstract Icon PDF Icon Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]
Marinissen, E J
Abstract Icon PDF Icon EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Abstract Icon PDF Icon Challenges and Emerging Solutions in Testing TSV-Based 2 1/2D-and 3D-Stacked ICs - Invited Paper [p. 1277]
Marinkovic, S
Abstract Icon PDF Icon Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Markov, I L
Abstract Icon PDF Icon RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Marongiu, A
Abstract Icon PDF Icon Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]
Abstract Icon PDF Icon Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Marques-Silva, J
Abstract Icon PDF Icon QBF-Based Boolean Function Bi-Decomposition [p. 816]
Marsh, G
Abstract Icon PDF Icon A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Martin, G
Abstract Icon PDF Icon Virtual Platforms: Breaking New Grounds [p. 685]
Martina, M
Abstract Icon PDF Icon A Network-on-Chip-based Turbo/LDPC Decoder Architecture [p. 1525]
Martinez Nova, A
Abstract Icon PDF Icon Optimization Intensive Energy Harvesting [p. 272]
Marwedel, P
Abstract Icon PDF Icon Multi-Objective Aware Extraction of Task-Level Parallelism Using Genetic Algorithms [p. 394]
Masera, G
Abstract Icon PDF Icon A Network-on-Chip-based Turbo/LDPC Decoder Architecture [p. 1525]
Masrur, A
Abstract Icon PDF Icon Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Masson, G
Abstract Icon PDF Icon UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications - Invited Paper [p. 1160]
Massouri, A
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Matthes, M
Abstract Icon PDF Icon Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Maurine, P
Abstract Icon PDF Icon Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
McConaghy, T
Abstract Icon PDF Icon Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Meder, K
Abstract Icon PDF Icon The Mobile Society - Chances and Challenges for Micro- and Power Electronics [p. 1]
Meissner, M
Abstract Icon PDF Icon Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Melikyan, V
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Meloni, P
Abstract Icon PDF Icon Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Melpignano, D
Abstract Icon PDF Icon P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Memik, G
Abstract Icon PDF Icon Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Meng, J
Abstract Icon PDF Icon Analysis and Runtime Management of 3D Systems with Stacked DRAM for Boosting Energy Efficiency [p. 611]
Mesman, B
Abstract Icon PDF Icon Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Messaoudi, J
Abstract Icon PDF Icon A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems [p. 751]
Meumeu Yomsi, P
Abstract Icon PDF Icon Challenges and New Trends in Probabilistic Timing Analysis [p. 810]
Meyer zu Bexten, V
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Meyer, M
Abstract Icon PDF Icon Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Miele, A
Abstract Icon PDF Icon An Adaptive Approach for Online Fault Management in Many-Core Architectures [p. 1429]
Milbredt, P
Abstract Icon PDF Icon Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Miller, B
Abstract Icon PDF Icon MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups [p. 1417]
Miller, C
Abstract Icon PDF Icon Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Mir, S
Abstract Icon PDF Icon Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Miremadi, S G
Abstract Icon PDF Icon SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Miryala, S
Abstract Icon PDF Icon IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]
Mishchenko, A
Abstract Icon PDF Icon Mapping into LUT Structures [p. 1579]
Mishra, P
Abstract Icon PDF Icon Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols [p. 3]
Misra, S K
Abstract Icon PDF Icon A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Mitea, O
Abstract Icon PDF Icon Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Mitra, S
Abstract Icon PDF Icon Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Mitra, T
Abstract Icon PDF Icon Online Scheduling for Multi-Core Shared Reconfigurable Fabric [p. 582]
Mittag, M
Abstract Icon PDF Icon Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Mittermaier, N
Abstract Icon PDF Icon EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Mohalik, S
Abstract Icon PDF Icon Verifying Timing Synchronization Constraints in Distributed Embedded Architectures [p. 200]
Mohammadi, A
Abstract Icon PDF Icon SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Mohanram, K
Abstract Icon PDF Icon High Performance Reliable Variable Latency Carry Select Addition [p. 1257]
Mojumder, N N
Abstract Icon PDF Icon Layout-Aware Optimization of STT MRAMs [p. 1455]
Molnos, A
Abstract Icon PDF Icon A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Monga, I
Abstract Icon PDF Icon Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers [p. 175]
Monteiro, J
Abstract Icon PDF Icon Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Morad, R
Abstract Icon PDF Icon Approximating Checkers for Simulation Acceleration [p. 153]
Morche, D
Abstract Icon PDF Icon Yield Optimization for Radio Frequency Receiver at System Level [p. 848]
Abstract Icon PDF Icon UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications - Invited Paper [p. 1160]
Morgan, M
Abstract Icon PDF Icon Fixed Origin Corner Square Inspection Layout Regularity Metric [p. 1397]
Moses, J
Abstract Icon PDF Icon PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Moshovos, A
Abstract Icon PDF Icon Toward Virtualizing Branch Direction Prediction [p. 455]
Mueller, W
Abstract Icon PDF Icon MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Mueller-Gritschneder, D
Abstract Icon PDF Icon Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level [p. 135]
Abstract Icon PDF Icon Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]
Muradore, R
Abstract Icon PDF Icon Predictive Control of Networked Control Systems over Differentiated Services Lossy Networks [p. 1245]
Muralimanohar, N
Abstract Icon PDF Icon CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Murillo, L
Abstract Icon PDF Icon Hybrid Simulation for Extensible Processor Cores [p. 288]
Mutlu, O
Abstract Icon PDF Icon Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]

N

Nagel,
Abstract Icon PDF Icon Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) [p. 1161]
Nahir, A
Abstract Icon PDF Icon Approximating Checkers for Simulation Acceleration [p. 153]
Nair, I
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Namyst, R
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Narayanan, R
Abstract Icon PDF Icon Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Narayanan, V
Abstract Icon PDF Icon Hazard Driven Test Generation for SMT Processors [p. 256]
Abstract Icon PDF Icon An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Nassar, M
Abstract Icon PDF Icon RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Nassery, A
Abstract Icon PDF Icon An Analytical Technique for Characterization of Transceiver IQ Imbalances in the Loop-Back Mode [p. 1084]
Nazhandali, L
Abstract Icon PDF Icon ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Nazin, S A
Abstract Icon PDF Icon Yield Optimization for Radio Frequency Receiver at System Level [p. 848]
Nelis, V
Abstract Icon PDF Icon Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]
Neogy, A
Abstract Icon PDF Icon Analysis and Design of Sub-Harmonically Injection Locked Oscillators [p. 1209]
Newby, T
Abstract Icon PDF Icon SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Newell, D
Abstract Icon PDF Icon PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Nicolaidis, M
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Nicolau, A
Abstract Icon PDF Icon VaMV: Variability-aware Memory Virtualization [p. 284]
Nikolov, H
Abstract Icon PDF Icon A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Nirmaier, T
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Novo, D
Abstract Icon PDF Icon Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]

O

O'Flynn, B
Abstract Icon PDF Icon Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Oertel, M
Abstract Icon PDF Icon Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Olivo, P
Abstract Icon PDF Icon A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Osello, A
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Osewold, C
Abstract Icon PDF Icon Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]
Oz, I
Abstract Icon PDF Icon Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Ozev, S
Abstract Icon PDF Icon An Analytical Technique for Characterization of Transceiver IQ Imbalances in the Loop-Back Mode [p. 1084]

P

Palermo, G
Abstract Icon PDF Icon Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Panagopoulos, G
Abstract Icon PDF Icon A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach [p. 1443]
Pang, G K H
Abstract Icon PDF Icon An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]
Papaefstathiou, I
Abstract Icon PDF Icon An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Parameswaran, S
Abstract Icon PDF Icon Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors [p. 875]
Park, M S
Abstract Icon PDF Icon An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Park, S
Abstract Icon PDF Icon Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Abstract Icon PDF Icon State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Park, S P
Abstract Icon PDF Icon Layout-Aware Optimization of STT MRAMs [p. 1455]
Parsa, R
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Partlo III, W E
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Patel, H D
Abstract Icon PDF Icon An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture [p. 659]
Patil, S
Abstract Icon PDF Icon Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Patti, E
Abstract Icon PDF Icon Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Pautet, L
Abstract Icon PDF Icon Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Pavlidis, V F
Abstract Icon PDF Icon Voltage Propagation Method for 3-D Power Grid Analysis [p. 844]
Pecheux, F
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Pedram, M
Abstract Icon PDF Icon Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]
Abstract Icon PDF Icon An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Abstract Icon PDF Icon Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric [p. 840]
Abstract Icon PDF Icon State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Pelissier, M
Abstract Icon PDF Icon UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications - Invited Paper [p. 1160]
Pellegrini, A
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Pelz, G
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Peng, Z
Abstract Icon PDF Icon Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]
Peraldi-Frati, M-A
Abstract Icon PDF Icon Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Peranandam, P
Abstract Icon PDF Icon An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Pereira, E
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Perin, G
Abstract Icon PDF Icon Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
Perlo, P
Abstract Icon PDF Icon Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Petracca, M
Abstract Icon PDF Icon Compositional System-Level Design Exploration with Planning of High-Level Synthesis [p. 641]
Petters, S M
Abstract Icon PDF Icon Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]
Pham, H-M
Abstract Icon PDF Icon UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Pidan, D
Abstract Icon PDF Icon Approximating Checkers for Simulation Acceleration [p. 153]
Piguet, C
Abstract Icon PDF Icon Fixed Origin Corner Square Inspection Layout Regularity Metric [p. 1397]
Pillement, S
Abstract Icon PDF Icon UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Pimentel, A D
Abstract Icon PDF Icon Design Space Pruning through Hybrid Analysis in System-level Design Space Exploration [p. 781]
Pineda de Gyvez, J
Abstract Icon PDF Icon Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems [p. 1048]
Pino, R E
Abstract Icon PDF Icon Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Pino, Y
Abstract Icon PDF Icon Logic Encryption: A Fault Analysis Perspective [p. 953]
Piscitelli, R
Abstract Icon PDF Icon Design Space Pruning through Hybrid Analysis in System-level Design Space Exploration [p. 781]
Pllana, S
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Plosila, J
Abstract Icon PDF Icon CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Plyaskin, R
Abstract Icon PDF Icon Virtual Platforms: Breaking New Grounds [p. 685]
Polian, I
Abstract Icon PDF Icon On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]
Pomata, S
Abstract Icon PDF Icon Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Poncino, M
Abstract Icon PDF Icon IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Abstract Icon PDF Icon Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]
Abstract Icon PDF Icon Application-Specific Memory Partitioning for Joint Energy and Lifetime Optimization [p. 364]
Pons, M
Abstract Icon PDF Icon Fixed Origin Corner Square Inspection Layout Regularity Metric [p. 1397]
Pontes, J
Abstract Icon PDF Icon An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design [p. 224]
Pop, P
Abstract Icon PDF Icon Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Poplavko, P
Abstract Icon PDF Icon SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Popovici, E
Abstract Icon PDF Icon Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Popp, R M
Abstract Icon PDF Icon Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Potkonjak, M
Abstract Icon PDF Icon Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Abstract Icon PDF Icon Optimization Intensive Energy Harvesting [p. 272]
Poulos, Z
Abstract Icon PDF Icon Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Pourshaghaghi, H R
Abstract Icon PDF Icon Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems [p. 1048]
Prakash, A
Abstract Icon PDF Icon An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture [p. 659]
Pravadelli, G
Abstract Icon PDF Icon Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Abstract Icon PDF Icon MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Prenat, G
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Prinetto, P
Abstract Icon PDF Icon A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Prochazka, W
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Provine, J
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Puaut, I
Abstract Icon PDF Icon Preemption Delay Analysis for Floating Non-Preemptive Region Scheduling [p. 497]

Q

Qian, Z
Abstract Icon PDF Icon A Flit-level Speedup Scheme for Network-on-Chips Using Self-Reconfigurable Bi-directional Channels [p. 1295]
Qin, X
Abstract Icon PDF Icon Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols [p. 3]
Qin, Z
Abstract Icon PDF Icon A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Quaglia, D
Abstract Icon PDF Icon Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Abstract Icon PDF Icon Predictive Control of Networked Control Systems over Differentiated Services Lossy Networks [p. 1245]
Quan, G
Abstract Icon PDF Icon Neighbor-Aware Dynamic Thermal Management for Multi-core Platform [p. 187]
Abstract Icon PDF Icon Harmonic Semi-Partitioned Scheduling for Fixed-Priority Real-Time Tasks on Multi-Core Platform [p. 503]
Quinton, S
Abstract Icon PDF Icon Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]
Abstract Icon PDF Icon Challenges and New Trends in Probabilistic Timing Analysis [p. 810]

R

Raabe, A
Abstract Icon PDF Icon Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Abstract Icon PDF Icon Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
Rafaila, M
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Raffo, L
Abstract Icon PDF Icon Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]
Ragel, R
Abstract Icon PDF Icon Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors [p. 875]
Rahimi, A
Abstract Icon PDF Icon Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]
Rahman, M
Abstract Icon PDF Icon Post-Synthesis Leakage Power Minimization [p. 99]
Rajeev, A C
Abstract Icon PDF Icon Verifying Timing Synchronization Constraints in Distributed Embedded Architectures [p. 200]
Rajendran, J
Abstract Icon PDF Icon Logic Encryption: A Fault Analysis Perspective [p. 953]
Rambo, E A
Abstract Icon PDF Icon On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Ramesh, S
Abstract Icon PDF Icon Verifying Timing Synchronization Constraints in Distributed Embedded Architectures [p. 200]
Abstract Icon PDF Icon An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Ranganathan, N
Abstract Icon PDF Icon Runtime Power Gating in Caches of GPUs for Leakage Energy Savings [p. 300]
Abstract Icon PDF Icon Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder [p. 721]
Ranjan, A
Abstract Icon PDF Icon PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations [p. 550]
Raviram, S
Abstract Icon PDF Icon An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Ray, S
Abstract Icon PDF Icon Scalable Progress Verification in Credit-Based Flow-Control Systems [p. 905]
Abstract Icon PDF Icon Mapping into LUT Structures [p. 1579]
Raychowdhury, A
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Rehman, S
Abstract Icon PDF Icon Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Reinhardt, A
Abstract Icon PDF Icon Yield Optimization for Radio Frequency Receiver at System Level [p. 848]
Reinig, H
Abstract Icon PDF Icon Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]
Reinman, G
Abstract Icon PDF Icon Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Richards, A
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Richter, M
Abstract Icon PDF Icon Test Pin Count Reduction for NoC-based Test Delivery in Multicore SOCs [p. 787]
Rimon, M
Abstract Icon PDF Icon Generating Instruction Streams Using Abstract CSP [p. 15]
Rinaudo, S
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Rivers, J
Abstract Icon PDF Icon EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Rivers, J A
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Rochange, C
Abstract Icon PDF Icon Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Rofouei, M
Abstract Icon PDF Icon Optimization Intensive Energy Harvesting [p. 272]
Rohfleisch, B
Abstract Icon PDF Icon Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Roncella, R
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Roop, P S
Abstract Icon PDF Icon Correct-by-Construction Multi-Component SoC Design [p. 647]
Rosenstiel, W
Abstract Icon PDF Icon Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Abstract Icon PDF Icon Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Abstract Icon PDF Icon Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies [p. 862]
Abstract Icon PDF Icon Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Rosiére, M
Abstract Icon PDF Icon An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Rosing, T S
Abstract Icon PDF Icon Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers [p. 175]
Abstract Icon PDF Icon TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs [p. 593]
Abstract Icon PDF Icon MAPG: Memory Access Power Gating [p. 1054]
Rottmann, A
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Rousseau, F
Abstract Icon PDF Icon Enhancing Non-Linear Kernels by an Optimized Memory Hierarchy in a High Level Synthesis Flow [p. 1130]
Rox, J
Abstract Icon PDF Icon Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]
Roy, K
Abstract Icon PDF Icon A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach [p. 1443]
Abstract Icon PDF Icon Layout-Aware Optimization of STT MRAMs [p. 1455]
Roy, S
Abstract Icon PDF Icon Runtime Power Gating in Caches of GPUs for Leakage Energy Savings [p. 300]
Abstract Icon PDF Icon An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Roychowdhury, J
Abstract Icon PDF Icon Analysis and Design of Sub-Harmonically Injection Locked Oscillators [p. 1209]
Rozic, V
Abstract Icon PDF Icon Low-Cost Implementations of On-the-Fly Tests for Random Number Generators [p. 959]
Rudolf, R
Abstract Icon PDF Icon Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Ruehrmair, U
Abstract Icon PDF Icon Characterization of the Bistable Ring PUF [p. 1459]
Ruggiero, M
Abstract Icon PDF Icon Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Rupnow, K
Abstract Icon PDF Icon Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]

S

Sabarad, J
Abstract Icon PDF Icon An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Sabena, D
Abstract Icon PDF Icon A New SBST Algorithm for Testing the Register File of VLIW Processors [p. 412]
Sabry, M M
Abstract Icon PDF Icon Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation [p. 599]
Abstract Icon PDF Icon A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Sadeghi, A-R
Abstract Icon PDF Icon PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Sadooghi-Alvandi, M
Abstract Icon PDF Icon Toward Virtualizing Branch Direction Prediction [p. 455]
Sadri, M
Abstract Icon PDF Icon Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]
Safari, S
Abstract Icon PDF Icon An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Sahlbach, H
Abstract Icon PDF Icon A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]
Sai, B
Abstract Icon PDF Icon A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Sainrat, P
Abstract Icon PDF Icon Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Salajka, V
Abstract Icon PDF Icon Towards New Applications of Multi-Function Logic: Image Multi-Filtering [p. 824]
Salcic, Z
Abstract Icon PDF Icon Correct-by-Construction Multi-Component SoC Design [p. 647]
Saletti, R
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
San Segundo Bello, D
Abstract Icon PDF Icon Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]
Sanchez, D
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Sanders, B
Abstract Icon PDF Icon Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Saponara, S
Abstract Icon PDF Icon Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Saranovac, L
Abstract Icon PDF Icon Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Sasao, T
Abstract Icon PDF Icon Row-Shift Decompositions for Index Generation Functions [p. 1585]
Sassone, A
Abstract Icon PDF Icon Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Satpathy, M
Abstract Icon PDF Icon An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Sauer, M
Abstract Icon PDF Icon On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]
Sawicki, J
Abstract Icon PDF Icon Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Scarpelli, A
Abstract Icon PDF Icon Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Schaumont, P
Abstract Icon PDF Icon ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Schindler, W
Abstract Icon PDF Icon Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models [p. 1179]
Schirner, G
Abstract Icon PDF Icon Application-Specific Power-Efficient Approach for Reducing Register File Vulnerability [p. 574]
Schirrmeister, F
Abstract Icon PDF Icon Virtual Platforms: Breaking New Grounds [p. 685]
Schlichtmann, U
Abstract Icon PDF Icon Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level [p. 135]
Abstract Icon PDF Icon Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]
Abstract Icon PDF Icon Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]
Abstract Icon PDF Icon Characterization of the Bistable Ring PUF [p. 1459]
Schmutzler, C
Abstract Icon PDF Icon On Demand Dependent Deactivation of Automotive ECUs [p. 69]
Schneider, R
Abstract Icon PDF Icon Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Schoenmaker, W
Abstract Icon PDF Icon Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Schrijen, G-J
Abstract Icon PDF Icon Comparative Analysis of SRAM Memories Used as PUF Primitives [p. 1319]
Schuchardt, M
Abstract Icon PDF Icon Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Sciuto, D
Abstract Icon PDF Icon An Adaptive Approach for Online Fault Management in Many-Core Architectures [p. 1429]
Scotti, S
Abstract Icon PDF Icon Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Sebastian, M
Abstract Icon PDF Icon Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Sebeke, C
Abstract Icon PDF Icon Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Sechen, C
Abstract Icon PDF Icon Post-Synthesis Leakage Power Minimization [p. 99]
Sekanina, L
Abstract Icon PDF Icon A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits [p. 715]
Abstract Icon PDF Icon Towards New Applications of Multi-Function Logic: Image Multi-Filtering [p. 824]
Sen, A
Abstract Icon PDF Icon Verification Coverage of Embedded Multicore Applications [p. 252]
Senepa, L
Abstract Icon PDF Icon SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Sengupta, R
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Sengupta, S
Abstract Icon PDF Icon A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Shafiee, A
Abstract Icon PDF Icon AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Shafique, M
Abstract Icon PDF Icon Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Shah, H
Abstract Icon PDF Icon Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
Shahid, M A
Abstract Icon PDF Icon Cross Entropy Minimization for Efficient Estimation of SRAM Failure Rate [p. 230]
Shao, Z
Abstract Icon PDF Icon 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]
Abstract Icon PDF Icon A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Sharifi, S
Abstract Icon PDF Icon TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs [p. 593]
Sharma, V
Abstract Icon PDF Icon Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
She, D
Abstract Icon PDF Icon Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Shen, C-C
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Shin, D
Abstract Icon PDF Icon State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Shin, J
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Shoaib, M
Abstract Icon PDF Icon A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Abstract Icon PDF Icon Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals [p. 437]
Silvano, C
Abstract Icon PDF Icon Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Sima, V-M
Abstract Icon PDF Icon Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Simons, M
Abstract Icon PDF Icon On Demand Dependent Deactivation of Automotive ECUs [p. 69]
Sinanoglu, O
Abstract Icon PDF Icon Logic Encryption: A Fault Analysis Perspective [p. 953]
Singh, M
Abstract Icon PDF Icon Multi-Token Resource Sharing for Pipelined Asynchronous Systems [p. 1191]
Singh, P
Abstract Icon PDF Icon Hazard Driven Test Generation for SMT Processors [p. 256]
Sinha, R
Abstract Icon PDF Icon Correct-by-Construction Multi-Component SoC Design [p. 647]
Sinkar, A A
Abstract Icon PDF Icon Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors [p. 1134]
Smolinski, R
Abstract Icon PDF Icon CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Soeken, M
Abstract Icon PDF Icon Debugging of Inconsistent UML/OCL Models [p. 1078]
Abstract Icon PDF Icon Eliminating Invariants in UML/OCL Models [p. 1142]
Song, W
Abstract Icon PDF Icon Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Sonza Reorda, M
Abstract Icon PDF Icon A New SBST Algorithm for Testing the Register File of VLIW Processors [p. 412]
Sotomayor Torres, C M
Abstract Icon PDF Icon Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Soudris, D
Abstract Icon PDF Icon A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Souissi, Y
Abstract Icon PDF Icon RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Sridhar, A
Abstract Icon PDF Icon Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation [p. 599]
Srivastav, M
Abstract Icon PDF Icon ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Stattelmann, S
Abstract Icon PDF Icon Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Stefan, R
Abstract Icon PDF Icon A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Stefanni, F
Abstract Icon PDF Icon Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Stefanov, T
Abstract Icon PDF Icon A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Steger, C
Abstract Icon PDF Icon Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Steinbach, D
Abstract Icon PDF Icon Guidelines for Model Based Systems Engineering [p. 159]
Steininger, A
Abstract Icon PDF Icon Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Steinmann, J
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Sterpone, L
Abstract Icon PDF Icon A New SBST Algorithm for Testing the Register File of VLIW Processors [p. 412]
Stipic, S
Abstract Icon PDF Icon TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Stoettinger, M
Abstract Icon PDF Icon Side Channel Analysis of the SHA-3 Finalists [p. 1012]
Abstract Icon PDF Icon Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models [p. 1179]
Stojilovic, M
Abstract Icon PDF Icon Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Stratigopoulos, H
Abstract Icon PDF Icon Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Stratigopoulos, H-G
Abstract Icon PDF Icon Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Straube, S
Abstract Icon PDF Icon Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Stripf, T
Abstract Icon PDF Icon A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]
Strong, R
Abstract Icon PDF Icon MAPG: Memory Access Power Gating [p. 1054]
Stuijk, S
Abstract Icon PDF Icon Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]
Abstract Icon PDF Icon Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Suaya, R
Abstract Icon PDF Icon An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems [p. 1203]
Sun, F
Abstract Icon PDF Icon Automatic Generation of Functional Models for Embedded Processor Extensions [p. 304]
Sun, G
Abstract Icon PDF Icon 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]
Abstract Icon PDF Icon Modeling and Design Exploration of FBDRAM as On-chip Memory [p. 1507]
Suri, B
Abstract Icon PDF Icon A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Swick, R
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]

T

Taatizadeh, P
Abstract Icon PDF Icon Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Tabkhi, H
Abstract Icon PDF Icon Application-Specific Power-Efficient Approach for Reducing Register File Vulnerability [p. 574]
Tahar, S
Abstract Icon PDF Icon Towards Improving Simulation of Analog Circuits Using Model Order Reduction [p. 1337]
Abstract Icon PDF Icon Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Tahoori, M B
Abstract Icon PDF Icon NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]
Abstract Icon PDF Icon Layout-Driven Robustness Analysis for Misaligned Carbon Nanotubes in CNTFET-based Standard Cells [p. 1609]
Tamiya, Y
Abstract Icon PDF Icon Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Tan, M
Abstract Icon PDF Icon Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Tan, S X-D
Abstract Icon PDF Icon Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]
Abstract Icon PDF Icon Parallel Statistical Analysis of Analog Circuits by GPU-accelerated Graph-based Approach [p. 852]
Abstract Icon PDF Icon A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation [p. 1349]
Tang, K-F
Abstract Icon PDF Icon Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Tang, Q
Abstract Icon PDF Icon Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Tang, W-C
Abstract Icon PDF Icon Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]
Tasic, B
Abstract Icon PDF Icon Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Teh, Y F
Abstract Icon PDF Icon A Flit-level Speedup Scheme for Network-on-Chips Using Self-Reconfigurable Bi-directional Channels [p. 1295]
Tehranipoor, M
Abstract Icon PDF Icon A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection [p. 1331]
Teich, J
Abstract Icon PDF Icon Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Abstract Icon PDF Icon Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Tenhunen, H
Abstract Icon PDF Icon CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Abstract Icon PDF Icon A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Tetzlaff, R
Abstract Icon PDF Icon Memristor Technology in Future Electronic System Design [p. 592]
Thach, D
Abstract Icon PDF Icon Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Thaler, A
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Thapliyal, H
Abstract Icon PDF Icon Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder [p. 721]
Theelen, B
Abstract Icon PDF Icon Model Checking of Scenario-Aware Dataflow with CADP [p. 653]
Theocharides, T
Abstract Icon PDF Icon Towards Accurate Hardware Stereo Correspondence: A Real-Time FPGA Implementation of a Segmentation-Based Adaptive Support Weight Algorithm [p. 703]
Thibault, S
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Thiele, D
Abstract Icon PDF Icon Optimizing Performance Analysis for Synchronous Dataflow Graphs with Shared Resources [p. 635]
Thomas, O
Abstract Icon PDF Icon Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Tischendorf, C
Abstract Icon PDF Icon Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Todorov, V
Abstract Icon PDF Icon Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller [p. 1066]
Todri, A
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Tokunaga, C
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Tomic, S
Abstract Icon PDF Icon TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Tong, D
Abstract Icon PDF Icon Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Abstract Icon PDF Icon S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Topcuoglu, H R
Abstract Icon PDF Icon Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Topham, N
Abstract Icon PDF Icon Predicting Best Design Trade-offs: A Case Study in Processor Customization [p. 1030]
Torres, L
Abstract Icon PDF Icon Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
Tosun, O
Abstract Icon PDF Icon Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Traff, J L
Abstract Icon PDF Icon Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Tretmans, J
Abstract Icon PDF Icon State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Tristl, M
Abstract Icon PDF Icon Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Trummer, R
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Tsai, H-P
Abstract Icon PDF Icon Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs [p. 1479]
Tschanz, J
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Tsui, C-Y
Abstract Icon PDF Icon A Flit-level Speedup Scheme for Network-on-Chips Using Self-Reconfigurable Bi-directional Channels [p. 1295]
Ttofis, C
Abstract Icon PDF Icon Towards Accurate Hardware Stereo Correspondence: A Real-Time FPGA Implementation of a Segmentation-Based Adaptive Support Weight Algorithm [p. 703]
Tung, S-Y
Abstract Icon PDF Icon Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Turturici, M
Abstract Icon PDF Icon Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]
Tuveri, G
Abstract Icon PDF Icon Exploiting Binary Translation for Fast ASIP Design Space Exploration on FPGAs [p. 566]

U

Ungerer, T
Abstract Icon PDF Icon Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Unsal, O
Abstract Icon PDF Icon TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]

V

Vahid, F
Abstract Icon PDF Icon MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups [p. 1417]
Valero, M
Abstract Icon PDF Icon TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
van Berkel, C H
Abstract Icon PDF Icon A Complexity Adaptive Channel Estimator for Low Power [p. 1531]
van der Leest, V
Abstract Icon PDF Icon Comparative Analysis of SRAM Memories Used as PUF Primitives [p. 1319]
van der Meijs, N
Abstract Icon PDF Icon Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Vandling, G
Abstract Icon PDF Icon EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Varman, P
Abstract Icon PDF Icon High Performance Reliable Variable Latency Carry Select Addition [p. 1257]
Vasicek, Z
Abstract Icon PDF Icon A SAT-based Fitness Function for Evolutionary Optimization of Polymorphic Circuits [p. 715]
Vatajelu, E I
Abstract Icon PDF Icon Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation [p. 1343]
Vaupel, M
Abstract Icon PDF Icon Virtual Platforms: Breaking New Grounds [p. 685]
Vega, A
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Veljkovic, F
Abstract Icon PDF Icon Low-Cost Implementations of On-the-Fly Tests for Random Number Generators [p. 959]
Veneris, A
Abstract Icon PDF Icon Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Abstract Icon PDF Icon Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Verbauwhede, I
Abstract Icon PDF Icon PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Abstract Icon PDF Icon Low-Cost Implementations of On-the-Fly Tests for Random Number Generators [p. 959]
Verma, N
Abstract Icon PDF Icon Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals [p. 437]
Vincent, P
Abstract Icon PDF Icon UWB: Innovative Architectures Enable Disruptive Low Power Wireless Applications - Invited Paper [p. 1160]
Vinco, S
Abstract Icon PDF Icon MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Violante, M
Abstract Icon PDF Icon An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation [p. 1433]
Virazel, A
Abstract Icon PDF Icon Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Vivet, P
Abstract Icon PDF Icon An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design [p. 224]
Vizzini, D
Abstract Icon PDF Icon Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Vladimerescu, A
Abstract Icon PDF Icon Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Voyiatzis, I
Abstract Icon PDF Icon Input Vector Monitoring on Line Concurrent BIST Based on Multilevel Decoding Logic [p. 1251]
Vyagrheswarudu, N
Abstract Icon PDF Icon PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations [p. 550]

W

Wajsbürt, F
Abstract Icon PDF Icon An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Walravens, C
Abstract Icon PDF Icon Design of a Low-Energy Data Processing Architecture for WSN Nodes [p. 570]
Wan, J
Abstract Icon PDF Icon Monitoring Active Filters under Automotive Aging Scenarios with Embedded Instrument [p. 1096]
Wang, C
Abstract Icon PDF Icon Extending the Lifetime of NAND Flash Memory by Salvaging Bad Blocks [p. 260]
Wang, C-Y
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Wang, H
Abstract Icon PDF Icon Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]
Abstract Icon PDF Icon Parallel Statistical Analysis of Analog Circuits by GPU-accelerated Graph-based Approach [p. 852]
Abstract Icon PDF Icon Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors [p. 1134]
Abstract Icon PDF Icon A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation [p. 1349]
Wang, J
Abstract Icon PDF Icon A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Wang, K
Abstract Icon PDF Icon S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Wang, L
Abstract Icon PDF Icon Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Wang, S
Abstract Icon PDF Icon Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Wang, S-C
Abstract Icon PDF Icon Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Wang, T
Abstract Icon PDF Icon A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Wang, X
Abstract Icon PDF Icon S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Abstract Icon PDF Icon Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Wang, Y
Abstract Icon PDF Icon Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]
Abstract Icon PDF Icon Runtime Power Gating in Caches of GPUs for Leakage Energy Savings [p. 300]
Abstract Icon PDF Icon State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Abstract Icon PDF Icon 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]
Abstract Icon PDF Icon A Block-Level Flash Memory Management Scheme for Reducing Write Activities in PCM-based Embedded Systems [p. 1447]
Abstract Icon PDF Icon An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]
Abstract Icon PDF Icon A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Wang, Z
Abstract Icon PDF Icon Accurate Source-Level Simulation of Embedded Software with Respect to Compiler Optimizations [p. 382]
Wassal, A G
Abstract Icon PDF Icon Double-Patterning Friendly Grid-Based Detailed Routing with Online Conflict Resolution [p. 1475]
Watanabe, Y
Abstract Icon PDF Icon Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Watt, J
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Weger, A J
Abstract Icon PDF Icon Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Wehn, N
Abstract Icon PDF Icon DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]
Abstract Icon PDF Icon An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Weis, C
Abstract Icon PDF Icon DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]
Abstract Icon PDF Icon An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Weiss, R
Abstract Icon PDF Icon Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Wenger, M
Abstract Icon PDF Icon Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Wenninger, J
Abstract Icon PDF Icon Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Werner, S
Abstract Icon PDF Icon Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Whitty, S
Abstract Icon PDF Icon A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]
Wilcock, R
Abstract Icon PDF Icon Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Wille, R
Abstract Icon PDF Icon Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]
Abstract Icon PDF Icon Debugging of Inconsistent UML/OCL Models [p. 1078]
Abstract Icon PDF Icon Eliminating Invariants in UML/OCL Models [p. 1142]
Williams, R S
Abstract Icon PDF Icon Memristor Technology in Future Electronic System Design [p. 592]
Wilson, P
Abstract Icon PDF Icon Automated Critical Device Identification for Configurable Analogue Transistors [p. 858]
Wong, H-S P
Abstract Icon PDF Icon Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Wong, N
Abstract Icon PDF Icon Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]
Abstract Icon PDF Icon An Operational Matrix-Based Algorithm for Simulating Linear and Fractional Differential Circuits [p. 1463]
Wong, W-F
Abstract Icon PDF Icon Extending the Lifetime of NAND Flash Memory by Salvaging Bad Blocks [p. 260]
Wu, H
Abstract Icon PDF Icon Model Checking of Scenario-Aware Dataflow with CADP [p. 653]
Wu, K-C
Abstract Icon PDF Icon Mitigating Lifetime Underestimation: A System-Level Approach Considering Temperature Variations and Correlations between Failure Mechanisms [p. 1269]
Wu, W
Abstract Icon PDF Icon Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Wu, Y-L
Abstract Icon PDF Icon Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]

X

Xhakoni, A
Abstract Icon PDF Icon Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]
Xie, L
Abstract Icon PDF Icon Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations [p. 1591]
Xie, Q
Abstract Icon PDF Icon Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]
Abstract Icon PDF Icon State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Xie, Y
Abstract Icon PDF Icon 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]
Abstract Icon PDF Icon Modeling and Design Exploration of FBDRAM as On-chip Memory [p. 1507]
Xie, Z
Abstract Icon PDF Icon Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Xing, X
Abstract Icon PDF Icon Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Xu, C
Abstract Icon PDF Icon Modeling and Design Exploration of FBDRAM as On-chip Memory [p. 1507]
Xu, Q
Abstract Icon PDF Icon On Effective TSV Repair for 3D-Stacked ICs [p. 793]
Abstract Icon PDF Icon Clock Skew Scheduling for Timing Speculation [p. 929]
Xu, Y
Abstract Icon PDF Icon Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Abstract Icon PDF Icon Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]

Y

Yakoushkin, S
Abstract Icon PDF Icon Hybrid Simulation for Extensible Processor Cores [p. 288]
Yang, G
Abstract Icon PDF Icon A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Yang, H
Abstract Icon PDF Icon A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Yang, J
Abstract Icon PDF Icon Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Yang, S
Abstract Icon PDF Icon Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Yang, X
Abstract Icon PDF Icon Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]
Yang, Y
Abstract Icon PDF Icon Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]
Yang, Y-C
Abstract Icon PDF Icon A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Yang, Y-S
Abstract Icon PDF Icon Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Ye, R
Abstract Icon PDF Icon Clock Skew Scheduling for Timing Speculation [p. 929]
Ye, Z
Abstract Icon PDF Icon Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Yeolekar, A
Abstract Icon PDF Icon An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Yi, J
Abstract Icon PDF Icon S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Yip, T G
Abstract Icon PDF Icon Challenges in Verifying an Integrated 3D Design [p. 167]
Yoo, S
Abstract Icon PDF Icon A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]
Abstract Icon PDF Icon Bloom Filter-based Dynamic Wear Leveling for Phase-Change RAM [p. 1513]
Yordanov, B
Abstract Icon PDF Icon Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Yu, H
Abstract Icon PDF Icon Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Abstract Icon PDF Icon A GPU-Accelerated Envelope-Following Method for Switching Power Converter Simulation [p. 1349]
Yu, W
Abstract Icon PDF Icon Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]
Yu, Z
Abstract Icon PDF Icon A Complexity Adaptive Channel Estimator for Low Power [p. 1531]
Yuan, F
Abstract Icon PDF Icon Clock Skew Scheduling for Timing Speculation [p. 929]
Yun, J
Abstract Icon PDF Icon Bloom Filter-based Dynamic Wear Leveling for Phase-Change RAM [p. 1513]

Z

Zaccaria, V
Abstract Icon PDF Icon Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Zaki, M H
Abstract Icon PDF Icon Towards Improving Simulation of Analog Circuits Using Model Order Reduction [p. 1337]
Abstract Icon PDF Icon Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Zambelli, C
Abstract Icon PDF Icon A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Zatt, B
Abstract Icon PDF Icon Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Zeng, H
Abstract Icon PDF Icon Task Implementation of Synchronous Finite State Machines [p. 206]
Zergainoh, N-E
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Zha, J
Abstract Icon PDF Icon Modeling and Testing of Interference Faults in the Nano NAND Flash Memory [p. 527]
Zhai, J T
Abstract Icon PDF Icon A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Zhang, C
Abstract Icon PDF Icon Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Abstract Icon PDF Icon Voltage Propagation Method for 3-D Power Grid Analysis [p. 844]
Abstract Icon PDF Icon Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Zhang, D
Abstract Icon PDF Icon A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Zhang, L
Abstract Icon PDF Icon A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Zhang, P
Abstract Icon PDF Icon Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Zhang, Y
Abstract Icon PDF Icon Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Abstract Icon PDF Icon Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Abstract Icon PDF Icon Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Zhao, B
Abstract Icon PDF Icon Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Zhao, S
Abstract Icon PDF Icon Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Zheng, C
Abstract Icon PDF Icon Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Zheng, L-R
Abstract Icon PDF Icon A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Zheng, Y
Abstract Icon PDF Icon Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Zhou, H
Abstract Icon PDF Icon Clock Skew Scheduling for Timing Speculation [p. 929]
Zimmermann, J
Abstract Icon PDF Icon Optimal Energy Management and Recovery for FEV [p. 683]
Abstract Icon PDF Icon Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies [p. 862]
Ziv, A
Abstract Icon PDF Icon Generating Instruction Streams Using Abstract CSP [p. 15]
Abstract Icon PDF Icon Approximating Checkers for Simulation Acceleration [p. 153]
Zjajo, A
Abstract Icon PDF Icon Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Zohner, M
Abstract Icon PDF Icon Side Channel Analysis of the SHA-3 Finalists [p. 1012]
Zorian, Y
Abstract Icon PDF Icon Design for Test and Reliability in Ultimate CMOS [p. 677]
Zou, Q
Abstract Icon PDF Icon 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]
Zou, Y
Abstract Icon PDF Icon Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Zuluaga, M
Abstract Icon PDF Icon Predicting Best Design Trade-offs: A Case Study in Processor Customization [p. 1030]
Zyulkyarov, F
Abstract Icon PDF Icon TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Groups: