DATE 2011

W5 3D Integration - Applications, Technology, Architechture, Design, Automation, and Test

Printer-friendly versionPDF version
Session Type: 
Fri, 2011-03-18
0830 - 1600
Location / Room: 

Yuan Xie, Pennsylvania State U, US
Damien Riquet, STMicroelectronics SA, FR
Nikolaos Minas, IMEC, BE


3D Integration is a promising technology for extending Moore's momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. But in order to produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges. The first and second edition of this workshop took place in conjunction with DATE 2009 and DATE 2010 (see and

The Workshop programme contains the following elements:

  • Two invited keynote addresses
  • Two sessions with in total six regular presentations
  • Two poster sessions
  • A panel session


0830Welcome Address
0850Keynote Address
Architecture and Design of 3DICs
Tanay Karnik, Intel, USA
0925Keynote Address>
Lower Cost Alternative to TSV Using ThruChip Interface (TCI)
Tadahiro Kuroda, Keio University, Japan
Session chair:  Dr. Yinhe Han (Chinese Academy of Science)
1030Electrical Perfomances of 3D TSV Channel and 3D Stacked PDN based on Hierarchical Models
Jun So Pak, Joohee Kim, Jonhhyun Cho, Heegon Kim, Kieyong Kim and Joungho Kim, KAIST, KR
1100Thermal Gradient Effects on Inductively Coupled 3-D ICs
Somayyeh Rahimian Omam, Vasilis F Pavlidis and Giovanni De Micheli, EPF Lausanne, CH
1130Thermal-aware Bus Architecture Flow for Three-Dimensional Microprocessors
Eren Kursun and Yuan Xie, IBM, US
Session chair: Dr Vassilios Gerousis (Cadence)
1300Variation-Aware Die-to-Die Bonding in Circuit-Partitioned 3D Integrated Circuits
Lei Zhangy, Jie Wangy and Yinhe Hany, Chinese Academy of Sciences, CN, Qiang Xuz, The Chinese University of Hong Kong, HK
1330Early Chip Planning Cockpit
Jeonghee Shin, IBM, US
14003D integration with TSV interconnects: Technology Trends & Market Analysis
Christophe Zinck, Yole Developpement, FR
1445SESSION 6: PANEL DISCUSSION   “Commercialization of 3D
Technology: How far are we?”
Moderator:  Damien Riquet (STMicroelectronics)
Erik Jan Marinissen  (IMEC)
Mark Scannell (CEA-LETI)
Yves Dodo (STMicroelectronics)
Michale Healy (IBM)
Vassilios Gerousis (Cadence)

Poster session:

  1. Verilog-A 3D Electro-Thermal Simulation of ICs
    Jean-Christophe KRENCKER, Jean-Baptiste KAMMERER, Yannick HERVÉ and Luc HÉBRARD
    Institut d'Électronique du Solide et des Systèmes (InESS)
  2. Modeling the Efficiency of Stacked Silicon Systems: Computational, Thermal and Electrical Performance
    Matt Grange, Axel Jantsch, Dinesh Pamunuwa and Roshan Weerasekera
    Lancaster University
  3. A 3D stack cost optimization floorplanning and routing approach
    Andy Heinig and Thomas Schuster
    Fraunhofer IIS/EAS and TU Braunschweig
  4. Centip3De: A 7-Layer 3D System With 128 ARM Cortex-M3 Cores and 256MB of DRAM
    David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wiekowski, Gregory Chen, Trevor Mudge, Dennis Sylvester, David Blaauw
    University of Michigan
  5. Z-Cut First Timing Driven Placement for TSV-Based 3D Ics
    Yi-Rong Chen and Hung-Ming Chen
    National Chiao Tung University, Hsinchu, Taiwan
  6. Dynamic Buffer Regulator for 3D Mesh Network-on-Chip
    Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, Chinese Academy of Sciences
  7. Thermal-aware Task Scheduling for Communication Energy Minimization on Homogeneous NoC-based 3D MPSoCs
    Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li, Chinese Academy of Sciences
  8. Rapid Evaluation of 3-D Interconnection Schemes
    K. Siozios, D. Diamantopoulos, H. Sidiropoulos, A. Papanikolaou, and D. Soudris, National Technical University of Athens
  9. Digital Signal Propagation in 3D Passive Interposer Interconnections
    Olivier Valorge, Maxime Rousseau, Francis Calmon, Christian Gontrand, Thierry Lacrevaz, Alexis Farcy, Jean Charbonnier, Christine Fuchs, Ian O’Connor and Lisa McIlrath, R3Logic France and CEA-LETI/MINATEC
  10. DFT Architecture for Multi-Tower 3D-SICs
    Chun-Chuan Chi - National Tsing-Hua University, Taiwan
    Erik Jan Marinissen - IMEC, Belgium
    Sandeep K. Goel - TSMC, USA
    Chengwen Wu - National Tsing-Hua University, Taiwan
  11. Comparative Cost Analysis of 3-D Integrated Circuits
    Roshan Weerasekera , Dinesh Pamunuwa , Matt Grange , Axel Jantsch, Andrew Richardson, Mark Scannel
    Lancaster University, Royal Institute of Technology (KTH), and CEA-Leti, Minatec Campus
  12. Cellular Processor Array Design In 3D Integrated Circuit Technology
    Alexey Lopich Piotr Dudek
    The University of Manchester
  13. CIT - An Efficient Topology for 3D Stacked Architectures
    Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
    University of Turku, Finland
  14. A meta-optimization approach to setup a 3D thermal-aware floorplanner
    Felipe Frantz, Lioua Labrak, Ian O'Connor
    Université de Lyon
  15. Fast Power Ground Noise Analysis for TSV based 3D MPSoC
    Shuai Tao, Yu Wang, Rui Cao, Ning Ren, Yuchun Ma, Jiang Xu, Huazhong Yang
    Tsinghua University, Beijing, China and CSE Dept, HKUST
  16. Thermal Management through Task Scheduling for 3D NoC
    Jiafang Wang, Han Wang, Jiajia Jiao
    Heilongjiang University, China and Shanghai Jiaotong University, China