DATE 2023 Accepted Papers

Congratulations to the authors and co-authors of the following regular papers and extended abstracts for the acceptance of your papers at DATE 2023! We look forward to meeting you in Antwerp at DATE 2023 during 17-19 April 2023. 

This is an early notification of acceptance! Further information will be sent to the authors by Monday, 21 November 2022 AoE at the latest.

We consider that you/your co-authors are committed to present the paper at the conference in Antwerp. We reserve the right to remove the paper from the proceedings if none of the authors/co-authors registers and presents the paper at the conference.

Regular Papers

Submission ID Title
90 PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy
121 FSL-HD: Accelerating Few-Shot Learning on ReRAM using Hyperdimensional Computing
368 Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy Constraints
441 A Decentralized Frontier Queue for Improving Scalability of Breadth-First-Search on GPUs
472 HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
762 High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation
904 Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications
153 HD-I-IoT: Hyperdimensional Computing for Resilient Industrial Internet of Things Analytics
463 Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor
508 Towards deep learning-based occupancy detection via WiFi sensing in unconstrained environments
466 Stateful Energy Management for Multi-Source Energy Harvesting Transient Computing Systems
724 Timely Fusion of Surround Radar/Lidar for Object Detection in Autonomous Driving Systems
841 Fully On-board Low-Power Localization with Multizone Time-of-Flight Sensors on Nano-UAVs
109 Energy-efficient Wearable-to-Mobile offload of ML inference for PPG-based Heart-Rate estimation
216 End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture Classification
118 Privacy-Preserving Neural Representation for Brain-Inspired Learning
194 ObfusLock: An Efficient Obfuscated Locking Framework for Circuit IP Protection
379 The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures
562 SheLL: Shrinking eFPGA Fabrics for Logic Locking
771 EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction
819 RTLock: IP Protection using Scan-Aware Logic Locking at RTL
882 Adversarial Attack on Hyperdimensional Computing-based NLP Applications
899 Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions
920 Privacy-by-Sensing with Time-domain Differentially-Private Compressed Sensing
515 A Lightweight and Adaptive Cache Allocation Scheme for Content Delivery Networks
660 TBERT: Dynamic BERT Inference with Top-k Based Predictors
932 Token Adaptive Vision Transformer with Efficient Deployment for Fine-Grained Image Recognition
84 HDGIM: Hyperdimensional Genome Sequence Matching on Unreliable Highly-Scaled FeFET
149 Quantum Measurement Discrimination using Cumulative Distribution Functions
150 SparseMEM: Energy-efficient Design for In-memory Sparse-based Graph Processing
301 Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network
376 AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips
482 Split Additive Manufacturing for Printed Neuromorphic Circuits
664 CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation
11 Multiphysics Design and Simulation Methodology for Dense WDM Silicon Photonics
197 Two-Stream Neural Network for Post-Layout Waveform Prediction
461 Quantization-Aware Neural Architecture Search with Hyperparameter Optimization for Industrial Predictive Maintenance Applications
68 Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative Nets
547 Efficient Approximation of Performance Spaces for Analog Circuits via Multi-Objective Optimization
666 Multidimensional Features Helping Predict Failures in Production SSD-Based Consumer Storage Systems
855 Perspector: Benchmarking Benchmark Suites
970 UHS: An Ultra-fast Hybrid Storage Consolidating NVM and SSD in Parallel
142 Efficient Hyperdimensional Learning with Trainable, Quantizable, and Holistic Data Representation
185 Smart Knowledge Transfer-based Runtime Power Management
319 SG-Float: Achieving Memory Access and Computational Power Reduction Using Self-Gating Float in CNN Accelerators
440 A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators
522 REDRAW: Fast and Efficient Hardware Accelerator with REDuced Reads And Writes for 3D UNet
540 Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads
549 Jumping Shift: A Logarithmic Quantization Method For Low-Power CNN Acceleration
1039 Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations
151 Maximizing Computing Accuracy on Resource-Constrained Architectures
278 MECALS: A Maximum Error Checking Technique for Approximate Logic Synthesis
394 GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate Computing
432 COMPACT: Co-processor for Multi-mode Precision-adjustable Nonlinear Activation Function
490 DeepCAM: A fully CAM-based inference accelerator with variable hash lengths for energy-efficient deep neural networks
596 Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior
600 Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion
812 PECAN: A Product-Quantized Content Addressable Memory Network
272 Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms
331 High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table
610 Narrowing The Synthesis Gap: Academic FPGA Synthesis Is Catching Up With The Industry
928 FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency Matrix
944 PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs
129 DTOC: integrating Deep-learning driven Timing Optimization into state-of-the-art Commercial EDA tool
130 Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility
159 RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization
223 Center-of-delay: a new metric to drive timing margin against spatial variation in complex SOCs
314 A Novel Delay Calibration Method Considering Interaction between Cells and Wires
404 Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions
427 Exact Synthesis Based on Semi-Tensor Product Circuit Solver
476 An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification
588 Fast STA Graph Partitioning Framework for Multi-GPU Acceleration
644 Computing Effective Resistances on Large Graphs Based on Approximate Inverse of Cholesky Factor
837 Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach
874 ISOP: Machine Learning Assisted Inverse Stack-Up Optimization for Advanced Package Design
982 Fast and Accurate Wire Timing Estimation Based on Graph Learning
1015 TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction
171 Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration
350 Mixed-Signal Memristor-based Iterative Montgomery Modular Multiplication
357 ODLPIM: A Write-Optimized and Long-Lifetime ReRAM-Based Accelerator for Online Deep Learning
898 SAT-Based Quantum Circuit Adaptation
909 Hardware Efficient Weight-Binarized Spiking Neural Networks
954 Ultra-Dense 3D Physical Design Enables New Architectural Design Points with Large Benefits
958 Memristor-Spikelearn: A Spiking Neural Network Simulator for Studying Synaptic Plasticity under Realistic Memristor Behaviors
119 OverlaPIM: Overlap Optimization for Processing In-Memory Neural Network Acceleration
408 TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation
434 Out-of-channel data placement for balancing wear-out and I/O workloads in RAID-enabled SSDs
492 AGDM:An Adaptive Granularity Data Migration Strategy for Hybrid Memory Systems
584 P-PIM: A Parallel Processing-in-DRAM Framework Enabling RowHammer Protection
615 Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement
825 PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration
885 End-to-End DNN Inference on a Massively Parallel In-Memory Computing Architecture
1042 PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM
169 Towards High-Level Synthesis of Quantum Circuits
214 MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR
566 High-Level Synthesis versus Hardware Construction
611 Benchmarking Large Language Models for Automated Verilog RTL Code Generation
621 PTP: Accelerate Application Launch via Predictive and Time-sharing Prefetching on Smartphones
859 Using High-Level Synthesis to model SystemVerilog procedural timing controls
981 R-LDPC: Refining  Behavior Descriptions in HLS to Implement High-throughput LDPC Decoder
16 par-gem5: Parallelizing gem5's Atomic Mode
170 Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-MPI
179 Dynamic Refinement of Hardware Assertion Checkers
397 STSearch: State Tracing-based Search Heuristics for RTL Validation
686 Processor Verification using Symbolic Execution: A RISC-V Case-Study
748 System-Level Simulator of eFlash-Based Compute-in-Memory Accelerators for Convolutional Neural Networks
665 An Automated Verification Framework for HalideIR-Based Compiler Transformations
832 ChiselFV: A Formal Verification Framework for Chisel
1013 Synthesis with Explicit Dependencies
80 Proteus: HLS based NoC Generator and Simulator
111 Minimizing Communication Conflicts in Network-On-Chip based Processing-In-Memory Architecture
449 XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers
605 MOELA: A Multi-Objective Evolutionary/Learning  Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms
30 UVMMU: Hardware-Offloaded Page Migration for Heterogeneous Computing
73 Exploiting Kernel Compression on BNNs
299 ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining
358 Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches
363 AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads
446 FastRW: A Dataflow-Efficient and Memory-Aware Accelerator for Graph Random Walk on FPGAs
465 Twin ECC: A Data Duplication Based ECC for Strong DRAM Error Resilience
530 Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers
593 PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows
622 CRSPU: Exploit Commonality of Regular Sparsity to Support Various Convolutions on Systolic Arrays
760 CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory
956 Atomic but Lazy Updating with Memory-mapped Files for Persistent Memory
158 Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7µW
180 Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits
236 Fast Performance Evaluation Methodology for High-speed Memory Interfaces
431 Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
623 SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility
685 MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors
941 AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells
92 Table Re-Computation Based Low Entropy Inner Product Masking Scheme
114 SCFI: State Machine Control-Flow Hardening Against Fault Attacks
120 Exploiting Short Application Lifetimes for Low Cost Hardware Encryption in Flexible Electronics
155 EASIMask - Towards Efficient, Automated, and Secure Implementation of Masking in Hardware
310 Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation
382 APUF production line faults: uniqueness and testing
401 Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack
775 Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP
895 Efficient Software Masking of AES through Instruction Set Extensions
914 A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs
968 Scalable scan-chain-based extraction of neural network models
222 Attacking ReRAM-based Architectures using Repeated Writes
266 Establishing Dynamic Secure Sessions for ECQV Implicit Certificates in Embedded Systems
274 Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs
316 Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs
360 MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS
370 Hardware Trojans in eNVM Neuromorphic Devices
400 SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels
419 Expanding In-Cone Obfuscated Tree for Anti SAT Attack
483 Run-time integrity monitoring of untrustworthy analog front-ends
513 SPOILER-ALERT: Detecting SPOILER Attack Using Cuckoo Filter
567 HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities
581 SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing
730 Long Range Detection of Emanation from HDMI Cables Using CNN and Transfer Learning
125 MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior
165 SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures
251 Liveness-Aware Checkpointing of Arrays for Efficient Intermittent Computing
518 SERICO: Scheduling Real-Time I/O Requests in Computational Storage Drives
528 Light Flash Write for Efficient Firmware Update on Energy-harvesting IoT Devices
785 Region-based Flash Caching with Joint Latency and Lifetime Optimization in Hybrid SMR Storage Systems
925 GEM-RL: Generalized Energy Management of Wearable Devices using Reinforcement Learning
1001 ViX: Analysis-driven Compiler for Efficient Low-Precision Differentiable Inference
178 ImpactTracer: Root Cause Localization in Microservices Based on Fault Propagation Modeling
208 PumpChannel: An Efficient and Secure Communication Channel for Trusted Execution Environment on ARM-FPGA Embedded SoC
361 Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems
459 On the Degree of Parallelism in Real-Time Scheduling of DAG Tasks
595 Timing Predictability for SOME/IP-based Service-Oriented Automotive In-Vehicle Networks
663 Analysis and Optimization of Worst-Case Time Disparity in Cause-Effect Chains
817 Data Freshness Optimization on Networked Intermittent Systems
34 Chameleon: Dual Memory Replay for Online Continual Learning on Edge Devices
275 PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation
279 Block Group scheduling : A General Precision-scalable NPU Scheduling Technique with Precision-aware Memory Allocation
292 FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks
303 Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous Signals
387 Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT Networks
607 NAF: Deeper Network/Accelerator Co-Exploration for Customizing CNNs on FPGA
656 ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for 8-Bit DNN Training
676 Class-based Quantization for Neural Networks
790 RoaD-RuNNer: Collaborative DNN partitioning and offloading on heterogeneous edge systems
840 Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs
47 Pipe-BD: Pipelined Parallel Blockwise Distillation
100 Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity
220 Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars
249 Mobile Accelerator Exploiting Sparsity of  Multi-Heads, Lines and Blocks in Transformers in Computer Vision
333 RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers
377 M5: Multi-modal Multi-Task Model Mapping on Multi-FPGA with Accelerator Configuration Search
565 Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems
669 SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement
858 HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling
984 AIRCHITECT: Automating Hardware Architecture and Mapping Optimization
166 A Safety-Guaranteed Framework for Neural-Network-Based Planners in Connected Vehicles under Communication Disturbance
952 Co-Design of Topology, Scheduling, and Path Planning in Automated Warehouses
14 Improving Reliability of Spiking Neural Networks through Fault Aware Threshold Voltage Optimization
88 Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search
306 Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool Flows
460 Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes
560 Device-Aware Test for Back-Hopping Defects in STT-MRAMs
471 Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in-Memory
586 Smart Hammering: A practical method of pinhole detection in MRAM memories
807 Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections
369 Security-Aware Approximate Spiking Neural Network
793 BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes
931 A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication



Extended Abstracts

Submission ID Title
552 DropDim: Incorporating Efficient Uncertainty Estimation into Hyperdimensional Computing
652 Towards Smart Cattle Farms: Automated Inspection of Cattle Health with Real-Life Data
823 Time Series-based Driving Event Recognition for Two Wheelers
720 A Coupled Battery State of Charge and VoltageModel for Optimal Control Applications
718 ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers
82 Comprehensive Analysis of Hyperdimensional Computing against Gradient Based Attacks
523 Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array
575 CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution
886 Warm-Boot Attack on Modern DRAMs
852 Content- and Lighting-Aware Adaptive Brightness Scaling for Improved Mobile User Experience
233 SARA: An Efficient and Configurable Softmax Engine for Attention Model with Versatile RRAM Crossbar
392 Value-based Reinforcement Learning using Efficient Hyperdimensional Computing
448 Structural Generation of Virtual Prototypes for Smart Sensor Development in SystemC-AMS from Simulink Models
675 A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation
57 Developing an Ultra-low Power RISC-V Processor for Anomaly Detection
162 MonTM: Monitoring-based Thermal Management for Mixed-Criticality Systems
183 TorchApprox: GPU-Accelerated Approximate Neural Networks for PyTorch
532 Exploiting assertions mining and fault analysis to guide RTL-level approximation
557 An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits
861 Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons
374 Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems
1035 Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks
218 Mask Optimization with Deep Reinforcement Learning
244 Routability Prediction using Deep Hierarchical Classification and Regression
286 Enabling Efficient Design Rule Checking with GPU Acceleration
318 Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement
603 A Two-stage PCB Routing Algorithm Using Polygon-based Dynamic Partitioning and MCTS
671 DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network
7 SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for Spiking Neural Network Acceleration
636 BOMIG: A Majority Logic Synthesis Framework for AQFP Logic
428 Branch Predictor Design for Ambient Energy Harvesting Nonvolatile Processors
617 Optimizing Data Migration for Garbage Collection in ZNS SSDs
632 ENASA: Towards Edge Neural Architecture Search based on CIM acceleration
268 Unlocking the Power of Machine Learning for Faster Package and Board PDN Convergence
302 EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI
601 SCCL: An open-source SystemC to RTL translator
945 SCORCH: Neural Architecture Search and Hardware Accelerator Co-design with Reinforcement Learning
297 FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing
546 Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric
561 Metric Temporal Logic with Resettable Skewed Clocks
842 Polynomial Formal Verification of Floating Point Adders
613 A Lightweight Congestion Control Technique for NoCs with Deflection Routing
224 Out-of-Step Pipeline for Gather/Scatter Instructions
576 MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster
702 Novel Efficient Synonym Handling Mechanism for Virtual-real Cache Hierarchy
1031 TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA
499 Debugging Low Power Analog Neural Networks for Edge Computing
911 Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays
322 Highlighting Two EM Fault Models while Analyzing a Digital Sensor Limitations
592 Transfer Learning with Pre-silicon Leakage Models
767 Deep-learning Model Extraction through Software-based Power Side-channel
789 A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power Gating
910 Low-Cost First-Order Secure Boolean Masking in Glitchy Hardware
86 You can read my code, but you can't execute it
629 Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation
976 TIPLock: Key-Compressed Logic Locking using Through-Input-Programmable Lookup-Tables
237 FAGC: Free Space Fragmentation Aware GC Scheme based on Observations of Energy Consumption
338 TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes
352 CFU Playground: A Hardware-Software Co-Design Framework for Tiny Machine Learning on FPGAs
255 WCET Analysis of Shared Caches in Multi-Core Architectures using Event-Arrival Curves
260 Resource Optimization with 5G Configured Grant Scheduling for Real-Time Applications
335 ADAPTIVE: Agent-Based Learning for Bounding Time in Mixed-Criticality Systems
202 Lattice Quantization
300 Mitigating Heterogeneities in Federated Edge Learning with Resource-independence Aggregation
346 Multispectral Feature Fusion for Deep Object Detection on Embedded NVIDIA Platforms
633 RankSearch: An Automatic Rank Search towards Optimal Tensor Compression for Video LSTM Networks on the Edge
32 Accelerating Inference of 3D-CNN on ARM Many-core CPU via Hierarchical Model Partition
116 CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks
486 BOMP-NAS: Bayesian Optimization Mixed Precision NAS
797 harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of Deep Neural Networks.
469 Polyglot Modal Models through Lingua Franca
531 DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation
653 READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction
717 High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology
820 Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection
308 Bitstream-Level Interconnect Fault Characterization for SRAM-based FPGAs
393 Compact test pattern generation for multiple faults in deep neural networks
1057 Reduce: A Framework for Reducing the Overheads of Fault-Aware Retraining