W10 Workshop on Open-Source Design Automation for FPGAs - OSDA

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Eddie Hung, University of British Columbia, CA (Contact Eddie Hung)
Christian Krieg, Vienna University of Technology, AT (Contact Christian Krieg)
Clifford Wolf, Symbiotic EDA, AT (Contact Clifford Wolf)

Programme Committee Members

, , (Contact )
Shane Fleming, Imperial College London, GB (Contact Shane Fleming)
Hipolito Guzman-Miranda, University of Sevilla, ES (Contact Hipolito Guzman-Miranda)
Steve Hoover, Redwood EDA, US (Contact Steve Hoover)
Dirk Koch, University of Manchester, GB (Contact Dirk Koch)
Mieszko Lis, University of British Columbia, CA (Contact Mieszko Lis)
Brent Nelson, Brigham Young University, US (Contact Brent Nelson)
Steffen Reith, RheinMain University of Applied Sciences, DE (Contact Steffen Reith)
Davide Rossi, University of Bologna, IT (Contact Davide Rossi)

Submission Deadline: December 17, 2018

Submission Link

FPGAs are increasingly finding themselves in huge data-centers as well as in the hands of hobbyists. However the wide availability of these high and low cost devices contrasts with the narrow ways in which one can access them -- through proprietary closed-source tools and IP -- which can hamper the realisation and deployment of novel FPGA-based applications and EDA innovations. Open-source is a proven and prevalent success when it comes to CPU and GPU silicon, and there are already efforts to drive reconfigurable silicon towards the same trend.

This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry. These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate "open access" for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions.

Extended motivation

Topics of interest at OSDA include, but are not limited to:

  • Open-source FPGA tools -- the latest developments, breakthroughs, challenges and surveys on the toolflows required to target real silicon parts: synthesis, simulation, place and route, etc.
  • Open-source IP for FPGAs -- contributions that enrich the IP ecosystem and reduce the need to "re-invent the wheel", e.g. PCIe and DDR controllers, debug infrastructure, etc.
  • Design methodologies provided as open-source -- such as alternative hardware description languages (e.g. derived from Python, Scala), domain specific languages (DSL), high level synthesis (HLS), asynchronous methods, and others.
  • Directions on where the open-source FPGA movement should go, current weaknesses in the toolchain, and/or perspectives from industry on how open-source can affect aspects of safety, security, verification, IP protection, time-to-market, datacenter/cloud infrastructure, etc.
  • Discussions and case studies on how to license, acquire funding, and commercialise technologies surrounding open-source hardware, which may be different to open software.

Important dates

Submission deadline December 17, 2018
Notification of acceptance January 14, 2019
Camera-ready final version   Feb 11, 2019
Workshop March 29, 2019

Submission details and requirements

Prospective authors are invited to submit original contributions (up to six pages), extended abstracts describing work-in-progress or position papers (not exceeding two pages), and demo proposals that would be of general interest. Papers must be submitted as an A4-sized PDF, in the IEEE conference format.

In line with OSDA's mission, we encourage and will favour submissions that make all artifacts used for experimentation (benchmarks, code, etc.) available for private peer-review. Accepted submissions are required to publish these artifacts under an OSI-approved (preferably permissive) license.

The proceedings of this workshop containing all accepted papers will be published on the open-access arXiv repository. Every accepted paper must have at least one author registered to the workshop by January 31.
Selected papers may also be considered for a special-issue journal; student authors may be eligible for travel assistance from our sponsors.


07:30W10.1Registration Desk opens
08:30W10.2Workshops start
09:00W10.4Keynote (TBD)
10:00W10.5Coffee break 1
10:30W10.6Invited Speaker (TBD)
11:00W10.7Session 1 (talk, posters, demos) TBD
12:00W10.8Lunch break
12:45W10.9Panel discussion: "How does one commercialise open-source EDA/IP?"

Andrea Borga, oliscience, NL, Contact
Ulrich Drepper, Red Hat, DE, Contact Ulrich Drepper
Clifford Wolf, Symbiotic EDA, AT, Contact Clifford Wolf


  • Andrea Borga (Oliscience, Netherlands) -- biography
  • Uli Drepper (Red Hat, Germany) -- biography
  • Clifford Wolf (Symbiotic EDA, Austria) -- biography

will be discussing whether it is possible to build a (stable!) business or research group around open-source -- when the things that you are building is ostensibly given away for free. Topics explored will be panellist's experiences with doing this, their opinions on the various open-source licenses (copyleft versus permissive) in the context of hardware, their views on whether open and closed-source can co-exist, and the momentum within the EU to mandate "open access" research.

13:30W10.10"VHDL Reuse: from Vendor Independence to Open Source" Daniel van der Schuur (ASTRON, Netherlands)

Daniel van der Schuur, ASTRON, NL, Contact Daniel van der Schuur

Talk synopsis:
ASTRONs mission is to make discoveries in radio astronomy happen. The high performance streaming data systems we build to do that naturally have FPGAs at their hearts. To balance project requirements, cost and availability of FPGA devices, ASTRON uses an approach that is both vendor and application independent. With generic, universal FPGA platforms (UniBoard, UniBoard2, Perentie), new science applications can take advantage of already available hardware. By also having a vendor independent VHDL library and tool flow, new FPGA hardware can also be adopted/developed with minimal firmware rework needed. This talk is about the advantages of vendor independence and how we chose to implement this, covering VHDL source code, vendor IP, library structures and simulation and synthesis tools. Another important aspect is the automated regression testing of the firmware library as it is updated on a daily basis. All this is made possible and structured by ASTRONs scripted tool flow, which is to be released as open source on OpenCores.org. Finally, this talk will cover how and why ASTRON is going to release its firmware library on OpenCores, and the technical challanges in doing so.

Speaker biography:
Daniel van der Schuur is a digital designer at the Netherlands Institute for Radio Astronomy (ASTRON). As ASTRON designs, builds and operates complex high performance hybrid (FPGA, GPU, CPU, fiber networks) systems to make new discoveries, Daniel is passionate about reducing the time to science - from streaming system design to VHDL implementation.

14:00W10.11Invited Speaker (TBD)
14:30W10.12Coffee break 2
15:00W10.13Session 2 (talk, posters, demos) TBD
16:00W10.14"UVVM - The fastest growing FPGA verification methodology world-wide!" Espen Tallaksen (Bitvis, Norway)

Espen Tallaksen, Bitvis, NO, Contact Espen Tallaksen

Talk synopsis:
On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with only minor adjustments and no extra cost. For an FPGA design we all know that the architecture - all the way from the top to the micro architecture - is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench. UVVM (the open source Universal VHDL Verification Methodology) was developed to solve this and will reduce the verification time significantly while at the same time improving the product quality. UVVM provides a very simple and powerful architecture that allow designers to build their own test harness much faster than ever before - using a mix of their own and open source verification components. UVVM also provides an architecture, methodology and library to allow VHDL verification components to be made extremely efficiently. And maybe the most important feature - UVVM allows the best possible testbench and test case overview using high level commands for both DUT interface control and synchronization. The great overview, maintainability, extensibility, modifiability and reuse has resulted in an extraordinary fast spread of this methodology - and according to the 2018 Wilson Research report UVVM was the by far fastest growing FPGA verification methodology over the last two years. UVVM is the new standardised VHDL testbench architecture, recommended by Doulos and backed by ESA (the European Space Agency) through a contract for further extension of the UVVM functionality. This presentation will show you how simple this is to understand, build and control. It will also show the latest features from the ESA project and further planned extensions.

Speaker biography

16:45W10.16Closing remarks
17:30W10.15Workshops end