W04 6th Workshop on Design Automation for Understanding Hardware Designs (DUHDE6)

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Date: 
2019-03-29
Time: 
08:30-17:00
Location / Room: 
TBA

Organisers

Christian Krieg, Vienna University of Technology, AT (Contact Christian Krieg)
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE (Contact Oliver Keszöcze)

Programme Committee Members

Maciej Ciesielski, University of Massachusetts, US (Contact Maciej Ciesielski)
Azadeh Davoodi, University of Wisconsin - Madison, US (Contact Azadeh Davoodi)
Görschwin Fey, Technische Universität Hamburg, DE (Contact Görschwin Fey)
Tara Ghasempouri, Tallinn University of Technology, EE (Contact Tara Ghasempouri)
Ian Harris, University of Californa Irvine, US (Contact Ian Harris)
Jan Malburg, German Aerospace Center, DE (Contact Jan Malburg)
Heinz Riener, EPFL, CH (Contact Heinz Riener)
Jannis Germany Stoppe, DFKI GmbH, DE (Contact Jannis Germany Stoppe)
Pramod Subramanyan, Indian Institute of Technology Kanpur, IN (Contact Pramod Subramanyan)
Georg Weissenbacher, Vienna University of Technology, AT (Contact Georg Weissenbacher)
Clifford Wolf, Symbiotic EDA, AT (Contact Clifford Wolf)
Cunxi Yu, EPFL, CH (Contact Cunxi Yu)

Understanding a hardware design can be a tough process. When entering a large team as a new member, when extending a legacy design, or when documenting a new design, a lack in understanding the details of a design is a major obstacle for productivity. In software engineering, topics like software maintenance, software understanding or reverse engineering are well established in the research community and partially tackled by tools. In the hardware area, the re-use of IP-blocks, the growing size of designs and design teams leads to similar problems. Understanding of hardware requires deep insight into concurrently operating units, optimizations to reduce the required area, and specially tailored functional units for a particular use. In hardware security, it is vital to verify properties for security-critical paths of a design, which includes to fully understand a design pre- and post-synthesis.

Topics

The workshop focus includes but is not limited to the following topics in design understanding:

  • Design descriptions from the formal specification level (FSL) to electronic system level(ESL) down to register transfer level (RTL)

  • Extraction of high-level properties

  • Knowledge extraction from design structures at any level of abstraction

  • Feature localization: Localization of code implementing specialized functionality

  • Data/Control path extraction

  • Reverse engineering

  • Innovative GUIs for design and verification

  • Analysis of interaction between hardware and software

  • Metrics for (open-source) intellectual property (IP) cores

  • Formal methods for design understanding

  • Machine learning for design understanding

  • Future applications of design understanding

Submissions may be extended abstracts of 2 pages or full papers of 6 pages in IEEE or ACM conference style. Informal proceedings will be distributed electronically. Please submit your contributions at: https://www.softconf.com/date19/DUHDe

Agenda

TimeLabelSession
07:30W04.1Registration Desk opens
08:30W04.2Workshops start
10:00W04.3Coffee break 1
12:00W04.4Lunch break
14:30W04.5Coffee break 2
17:00W04.6Workshops end