W04 Design Automation for Understanding Hardware Designs (DUHDE5)

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Konferenz 4

Understanding a hardware design is tough. When entering a large team as a new member, when extending a legacy design, or when documenting a new design, lacks in understanding the details of a design are major obstacles for productivity. In software engineering topics like software maintenance, software understanding, reverse engineering are well established in the research community and partially tackled by tools. In the hardware area the re-use of IP-blocks, the growing size of designs and design teams leads to similar problems, which mostly have yet to be solved by the hardware community.

The core audience are practitioners working in circuit design and to researchers interested in design automation as well as researchers and/or industry representatives from the fields of visualization and natural language processing.

It is not limited to the following topics in design understanding but includes:

  • Design descriptions from the ESL down to RTL
  • Extraction of high-level properties
  • Localization of code implementing particular functionality
  • Hardware design evolution : feature integration, feature interactions
  • Innovative GUIs for designs
  • Visualization of large scale designs
  • Managing documentation of hardware designs
  • Analysis of natural language documents and their connections to hardware implementations
  • Scalable approaches to design understanding

Programme Committee:

  • Eli Arbel IBM, Haifa Research Lab, IL
  • Lyes Benalycherif ST Microelechtronics, FR
  • Rüdiger Ehlers University of Bremen, DE
  • Görschwin Fey Hamburg University of Technology, DE
  • Christopher B. Harris Auburn University, US
  • Ian G. Harris UC Irvine, US
  • Oliver Keszöcze, University of Bremen, DE
  • Christian Krieg Vienna University of Technology, AT
  • Tun Li National University of Defense Technology, Changsha, CN
  • Matthieu Moy Université Claude Bernard Lyon 1, FR
  • Christos Papachristou Case Western Reverse University, US
  • Mathias Soeken EPFL, CH
  • Georg Weissenbacher Vienna University of Technology, AT
  • Francis Wolff Case Western Reserve University, US


08:30W04.1Design Understanding for Risk Reduction
08:30W04.1.1Design Risk Analysis Based on Version Control Data
Raviv Gal, IBM Haifa, IL

09:30W04.1.2A Test Register Assignment Method to Reduce the Number of Test Patterns Using Controller Augmentation
Syun Takeda1, Toshinori Hosokawa1, Hiroshi Yamazaki1 and Masayoshi Yoshimura2
1College of Industrial Technology, Nihon University, JP; 2Kyoto Sangyo University, JP

09:45W04.1.3A Secure Design Method to Detect for Trojan Circuit inserted in Manufacturing Process
Yoshinobu Okuda, Kohei Ohyama and Masayoshi Yoshimura, Kyoto Sangyo University, JP

10:30W04.2Turning Data into Knowledge: Tools and Applications I
10:30W04.2.1SymbiYosys: Investigating and Verifying Hardware Designs with Formal Open Source Tools
Clifford Wolf, TU Wien, AT

11:30W04.2.2Modeling Heterogeneous Embedded Systems with TTool
Daniela Genius1, Marie-Minerve Louerat1, Francois Pecheux1, Ludovic Apvrille2 and Haralampos Stratigopoulos1
1UPMC/LIP6, FR; 2System-on-Chip Laboratory (LabSoC), FR

13:00W04.3Turning Data into Knowledge: Tools and Applications II
13:00W04.3.1UMLAUT: Synthesis of Natural Language from Constrained UML Models
Martin Ring1, Jannis Stoppe2 and Rolf Drechsler3
1Cyber-Physical Systems, DFKI GmbH, DE; 2German Aerospace Center (DLR), Institute for the Protection of Maritime Infrastructures, DE; 3University of Bremen/DFKI GmbH, DE

13:30W04.3.2Subtree Identification for Generating Assertions from Natural Language Descriptions
Ian Harris, University of Californa Irvine, US

14:00W04.3.3Time-stamps for Hardware Simulation Models Accurate Time-back Annotation
Rehab Massoud1, Jannis Stoppe2 and Rolf Drechsler3
1Group of Computer Architecture, University of Bremen, DE; 2German Aerospace Center (DLR), Institute for the Protection of Maritime Infrastructures, DE; 3University of Bremen/DFKI GmbH, DE

15:00W04.4Current and Future Techniques
15:00W04.4.1Unconventional Computing - What, Why and How
Jan Madsen, Technical University of Denmark, DK

16:00W04.4.2PGSL: Identifying Functional Primitives in Hardware Description Language (HDL) Specifications
Christian Krieg, Martin Mosbeck, Clifford Wolf and Axel Jantsch, TU Wien, AT

16:30W04.4.3Execution Environment for Dynamic Software Runtime Examination
Kenneth Schmitz1, Oliver Keszöcze1, Jannis Stoppe2 and Rolf Drechsler3
1University of Bremen, DE; 2German Aerospace Center (DLR), Institute for the Protection of Maritime Infrastructures, DE; 3University of Bremen/DFKI GmbH, DE