W03 4th Workshop on Design Automation for Understanding Hardware Designs DUHDe 2017

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Date: 
2017-03-31
Time: 
08:30-17:30
Location / Room: 
TBA

Organisers

Ian Harris, University of Californa Irvine, US (Contact Ian Harris)
Mathias Soeken, EPFL, CH (Contact Mathias Soeken)

The design process is essentially a creative process which is reliant on the ability of designers to balance the interactions between a complex set of constraints to arrive at successful solutions. In order for designers to manage this task, they must collectively have a complete understanding of the behavior of the system, the mapping between behavior and structure, and the impact of each design feature on constraints such as power, performance, cost, and security. Design tasks require reasoning across multiple levels of abstraction in order to determine the impact of high-level design decisions, or to trace a design characteristic back to the feature which caused it. In a real design, cross-abstraction reasoning is difficult because the relationships between the different abstractions of a design are not captured. Designer time is expended discovering these cross-abstraction relationships in order to perform design, verification, and maintenance tasks. This workshop will present the state-of-the-art in Design Understanding, research in approaches to provide designers with the design information needed in a concise and straightforward way.

Agenda

TimeLabelSession
08:30W03.1Welcome
08:35W03.2Invited Talk: Dr. Barbara Jobstmann EPFL, Lausanne, Switzerland
08:35W03.2.1Title: TBA
Barbara Jobstmann, EPFL, CH

09:35W03.3Research Session 1
09:35W03.3.1ELVE: An Interactive and Extensible Visualisation Tool for Logic Circuits
Gregoire Hirt1, Ana Petkovska1 and Paolo Ienne2
1EPFL, CH; 2EPFL I&C LAP, CH

10:00W03.4Coffee Break
10:30W03.5Invited Talk: Dr. Martin Monperrus University of Lille & INRIA, France
10:30W03.5.1Title: TBA
Martin Montperrus, University of Lille & INRIA, FR

11:30W03.6Research Session 2
11:30W03.6.1Mining Latency Guarantees for RT-level Designs
Jan Malburg1, Heinz Riener2 and Goerschwin Fey3
1German Aerospace Center, DE; 2DLR, DE; 3Univ. of Bremen, DE

12:00W03.7Lunch Break
13:00W03.8Research Session 3
13:00W03.8.1Verilog2GEXF Dynamic Large Scale Circuit Visualization
Kenneth Schmitz1, Jannis Stoppe2 and Rolf Drechsler3
1University of Bremen, DE; 2Universität Bremen, DE; 3Department of Mathematics and Computer Science, University of Bremen, GermanyCyber-Physical Systems, DFKI GmbH, Bremen, Germany, DE

13:25W03.8.2Computing Exact Fault Candidates Incrementally
Heinz Riener1 and Goerschwin Fey2
1DLR, DE; 2Univ. of Bremen, DE

13:50W03.8.3A Human-Centered Approach to Routing for Digital Microfluidic Biochip
Oliver Keszöcze1, Andre Pols2 and Rolf Drechsler3
1University of Bremen, DE; 2University of Bremen, AD; 3Department of Mathematics and Computer Science, University of Bremen, GermanyCyber-Physical Systems, DFKI GmbH, Bremen, Germany, DE

14:15W03.8.4Making Waveforms Great Again
Jannis Stoppe1 and Rolf Drechsler2
1Universität Bremen, DE; 2Department of Mathematics and Computer Science, University of Bremen, GermanyCyber-Physical Systems, DFKI GmbH, Bremen, Germany, DE

14:40W03.9Coffee Break
15:00W03.10Invited Talk: Shalini Ghosh, SRI International, USA
15:00W03.10.1Title: TBA
Shalini Ghosh, SRI International, US

16:00W03.11Research Session 4
16:00W03.11.1A Natural Language Interface to Design Cyber-Physical Systems
Sophia Balkovski1 and Ian Harris2
1University of California Irvine, US; 2University of Californa Irvine, US

16:25W03.11.2On Identifying Functional Primitives in Hardware Description Language (HDL) Specifications
Christian Krieg1, Martin Mosbeck2, Clifford Wolf2 and Axel Jantsch3
1Institute of Computer Technology, Vienna University of Technology, AT; 2TU Wien, AT; 3Technische Universität Wien, AT