W02 Emerging Memory Solutions & Applications - Technology, Manufacturing, Architectures, Design, Automation and Test

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Location / Room: 
Konferenz 2

General Chair

Said Hamdioui, Delft University of Technology, NL (Contact Said Hamdioui)

Panel Chair

Ian O'Connor, Lyon Institute of Nanotechnology, FR (Contact Ian O'Connor)

Publicity Chair

Matthias Jung, Fraunhofer IESE, DE (Contact Matthias Jung)

Programme Committee Co-Chairs

Christian Weis, University of Kaiserslautern, DE (Contact Christian Weis)
Bastien Giraud, CEA LETI, FR (Contact Bastien Giraud)

Publication Chair

Jean-Philippe Noel, CEA-Leti, FR (Contact Jean-Philippe Noel)

Steering Committee Member

Erik Jan Marinissen, IMEC, BE (Contact Erik Jan Marinissen)

Evolving memory technologies are triggering intense interdisciplinary activities; they have the potential to provide many benefits, such as energy efficiency, density, re-configurability, non-volatility, novel computational structures and approaches, massive parallelism, etc. And therefore overcome both technology and design limitations (e.g., leakage and memory wall) to answer the requirements of today's and future applications such as IoT, big-data, healthcare, etc. These characteristics may force to deeply revisit existing computing and storage paradigms.

This workshop (third edition) aims at providing a forum to discuss challenges, trends, solutions and applications of these rapidly evolving memory technologies by gathering researchers and engineers from academia and industry; it also aims at creating a unique network of competence and experts in all aspects of emerging memory solutions and technologies including manufacturing, architectures, design, automation and test.

Subjects of Interest

You are invited to participate and submit your contributions to the DATE 2018 Friday Workshop on Emerging Memory Solutions. The areas of interest include (but are not limited to) the following topics:

  • Volatile embedded memories (DRAM, SRAM, CAM etc.),
  • Advanced non-volatile memories (3D Flash, ReRAM, PCM, MRAM, STT-MRAM etc.),
  • Memories based on emerging devices/technologies (TFET, nanowires, CNTs, etc.), 3D stacking of memories,
  • Logic and arithmetic designs based on emerging memristive devices,
  • Application-specific memory solutions such as near memory computing,
  • Computing paradigms based on emerging memristive devices such as neuromorphic computing, computing-in-memory,
  • Automation, compilers, programming models, etc. for the above designs and architectures.

Program and Panel

This one-day event will consist of two plenary keynotes, regular and poster presentations, and a panel session. The panel of the workshop will be about the topic "Deep Learning: what is the best memory to choose?". We are looking forward to a very lively discussion.



Said Hamdioui, Delft University of Technology, NL, Contact Said Hamdioui

08:40W02.1.1Welcome Address
Christian Weis, University of Kaiserslautern, DE


Christian Weis, University of Kaiserslautern, DE, Contact Christian Weis

08:45W02.2.1"Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation"
Onur Mutlu, ETHZ, CH

Abstract: Today's systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in systems that cause performance, scalability and energy bottlenecks. Conventional memory technology is facing many scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of slightly higher cost. The emergence of 3D-stacked memory plus logic as well as the adoption of error correcting codes inside the latest DRAM chips are an evidence of this trend.

In this talk, I will discuss some recent research that aims to practically enable computation close to data. After motivating trends in applications as well as technology, we will discuss at least two promising directions: 1) performing massively-parallel bulk operations in memory by exploiting the analog operational properties of DRAM, with low-cost changes, 2) exploiting the logic layer in 3D-stacked memory technology in various ways to accelerate important data-intensive applications. In both approaches, we will discuss relevant cross-layer research, design, and adoption challenges in devices, architecture, systems, and programming models. Our focus will be the development of in-memory processing designs that can be adopted in real computing platforms at low cost.

09:30W02.3Invited Talk about Emerging Neuromorphic Applications

Pascal Vivet, CEA-Leti, FR, Contact Pascal Vivet

09:30W02.3.1SpiNNaker2: Energy Efficient Neuromorphic Computing in 22nm FDSOI CMOS
Sebastian Höppner, Technische Universität Dresden, DE

10:00W02.4Coffee Break and Poster Session

Bastien Giraud, CEA-Leti, FR, Contact Bastien Giraud

10:30W02.5Industry Talk

Ian O'Connor, Ecole Centrale de Lyon, FR, Contact Ian O'Connor

10:30W02.5.1Applications of phase-change memory in non-von Neumann computing
Manuel Le Gallo, IBM, CH

11:00W02.6Panel about "Deep Learning: what is the best Memory to choose?"

Ian O'Connor, Ecole Centrale de Lyon, FR, Contact Ian O'Connor

Elisa Vianello, CEA-Leti, FR, Contact Elisa Vianello
Andrew J. Walker, Spin Transfer Technologies, Schiltron Corp., US, Contact Andrew J. Walker
Manuel Le Gallo, IBM, CH, Contact Manuel Le Gallo

The bridge between technology and applications is challenging. But that is exactly what this topic is about.
Our discussion will take into consideration Deep Learning and AI (different flavors of neural networks) as used in current available Smartphones and HPC systems.

  • How commodity technologies such as Flash, DRAM, 3D NAND are still suitable to support this demanding applications?
  • How this fits together in the future?
  • Can the technology and the design of memories help to improve?
  • What about Emerging Memories, do they fit? What are the best candidates?
12:00W02.7Lunch Break

Said Hamdioui, Delft University of Technology, NL, Contact Said Hamdioui

13:00W02.8.1"Memory-Centric Architectures for Artificial Intelligence"
Paul Franzon, NC State University, US

Abstract: There is much current interest in building custom accelerators for machine learning and machine intelligence algorithms.  However, at their root, many of these algorithms are very memory intensive in both capacity and bandwidth needs.  Thus there is a need for memory-processor codesign to obtain the most of these algorithms.  This talk presents multiple options to achieve high performance.

A 3DIC logic on memory stack has been designed to support the compute needs for multiple parallel inference engines running deep networks simultaneously, for example as would be needed for autonomous vehicles.  The DRAM is adopted from the Tezzaron DiRAM4 but supports over 130 Tbps of memory bandwidth with potential for 64 GB of capacity.

A Processor In Memory architecture with Application Specific Instruction features has been designed to support Sparse Hierarchical Temporal algorithms that permit in-situ learning.   These achieve an improvement in performance over a GPU implementation of over 20x and a power efficiency improvement of over 500x. 

Currently we are designing 2.5D versions of these accelerators as well as accelerators for quantized deep learning and Long Short Term Memory (LSTM) algorithms.  Preliminary results from this activity will be presented.

13:30W02.9Special Session I on "In-Memory Computing"

Said Hamdioui, Delft University of Technology, NL, Contact Said Hamdioui

13:30W02.9.1Memristive Memory Processing Unit (mMPU) for Real Processing in Memory
Nishil Talati, TECHNION, IL

13:50W02.9.2The Processing In Memory Revolution
Fabrice Devaux, UPMEM SAS, FR

14:10W02.9.3Conceptual design of a RISC-V compatible processor core using ternary arithmetic unit with memristive MLC storage
Dietmar Fey, FAU, DE

14:30W02.10Coffee Break and Poster Session

Bastien Giraud, CEA-Leti, FR, Contact Bastien Giraud

15:00W02.11Special Session II on "Emerging RRAMs and Alternatives"

Bastien Giraud, CEA-Leti, FR, Contact Bastien Giraud

15:00W02.11.1Challenges for Memristive Circuit Design
Anne Siemon, RWTH, DE

15:20W02.11.2Reliability Modeling Framework for Emerging STT-MRAM
Rajendra Bishnoi, Karlsruhe Institiute of Technology, DE

15:40W02.11.3Compact modeling of resistive switching memories
Marc Bocquet, IM2NP, FR

16:00W02.12Open Call Paper Session

Matthias Jung, Fraunhofer IESE, DE, Contact Matthias Jung

16:00W02.12.1Quantifying the Performance Overhead of NVML
William Wang, ARM, GB

16:15W02.12.2RRAM-based Automata Processor
Jintao Yu, Delft University of Technology, NL

16:27W02.12.3Energy Efficient DRAM Cache with Unconventional Row Buffer Size
Nyunyi M. Tshibangu, NCSU, US

16:39W02.12.4A 3-D Priority Address Encoder for 3-D Content Addressable Memories
Jin-Fu Li, NCU, TW

16:51W02.12.5Asynchronous Ultra Wide Voltage Range Two-Port SRAM Circuit for Fast Wake-up IoT Platform
Réda Boumchedda, STMicroelectronics, FR