W02 Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test

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Date: 
2017-03-31
Time: 
0830-17:00
Location / Room: 
2A

General Chair

Christian Weis, University of Kaiserslautern, DE (Contact Christian Weis)

Programme Chair

Bastien Giraud, CEA-Leti, Minatec, FR (Contact Bastien Giraud)

Panel Chair

Ian O'Connor, Ecole Centrale de Lyon, FR (Contact Ian O'Connor)

Publicity Chair

Matthias Jung, University of Kaiserslautern, DE (Contact Matthias Jung)

Proceedings Chair

Jean-Philippe Noel, CEA-Leti, FR (Contact Jean-Philippe Noel)

Steering Committee Member

Erik Jan Marinissen, IMEC, BE (Contact Erik Jan Marinissen)

Scope

Memory manufacturing, architectures, design and test were deeply investigated in-depth to address issues linked to technology scaling such as increasing static power, maximum operating frequency and the gap between logic and memory minimum voltages. Various emerging memories solutions have appeared in recent years with the aim to replace either partially or completely already existing memories in order to overcome both technology and design related limitations while giving answers to the aggressive requirements of many different applications. The goal of this Workshop is to bring together researchers, practitioners, designers and other people interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss the future challenges and trends.

Subjects of interest

You are invited to participate and submit your contributions to DATE 2017 Friday Workshop on Emerging Memory Solutions. The areas of interest include (but are not limited to) the following topics:

  • Volatile memory design (SRAM, DRAM, CAM, etc.)
  • Non-Volatile memory design (ReRAM, Flash, PCM, MRAM, etc.)
  • Applications of emerging devices in memories (TFETs, CNTs, nanowires, etc.)
  • 3D memories (volatile and non-volatile)
  • In-Memory and Near-Memory Processing
  • Memory Application for emerging markets
  • Memory test, BIST and debug techniques
  • Applications, products and prototypes of new memories

Panel

The panel of the workshop will be about the topic "Can We Jump over the Memory Wall with In-Memory Computing?". We looking forward to a very lively discussion moderated by our panel chair Ian O'Connor.

Agenda

TimeLabelSession
08:30W02.1Opening and 1st Keynote

Chair:
Christian Weis, University of Kaiserslautern, DE, Contact Christian Weis

08:30W02.1.1Welcome Addresss
Christian Weis, University of Kaiserslautern, DE

08:35W02.1.2Keynote: "Tomorrow's Memory Systems"
Bruce Jacob, University of Maryland, US

In the future new memory systems and technologies will appear, but what are the implications on the programming models in a few years from now.

Prof. Bruce Jacob:

Bruce Jacob is a Keystone Professor of Electrical and Computer Engineering and former Director of Computer Engineering at the University of Maryland in College Park. He received the AB degree in mathematics from Harvard University in 1988 and the MS and PhD degrees in CSE from the University of Michigan in Ann Arbor in 1995 and 1997, respectively. He holds several patents in the design of circuits for electric guitars and started a company around them. He also worked for two successful startup companies in the Boston area: Boston Technology and Priority Call Management. At Priority Call Management he was the initial system architect and chief engineer. He is a recipient of a US National Science Foundation CAREER award for his work on DRAM, and he is the lead author of an absurdly large book on the topic of memory systems. His research interests include system architectures, memory systems, operating systems, and electric guitars.

09:15W02.2Special Session on Emerging Memory Applications

Chair:
Pascal Vivet, CEA-Leti, FR, Contact Pascal Vivet

09:15W02.2.1Narrower-purpose Computing for Efficient Near-Memory Processing
Stephan Diestelhorst, ARM, GB

09:40W02.2.2Scalable Deep-Learning with Smart Memory Cubes
Erfan Azarkhish, DEIS, University of Bologna, Bologna, IT

10:00W02.3Coffee Break and Poster Session I

See for the Poster List below.

10:30W02.4Invited Talk and Panel

Moderator:
Ian O'Connor, Ecole Centrale de Lyon, FR, Contact Ian O'Connor

10:30W02.4.1Cortical Processors and Memories!
Paul Franzon, NC State University, US

Abstract

There has been strong recent interest in machine learning algorithms that are capable of unsupervised learning and incremental learning. A subset of these algorithms are cortically inspired, that is inspired by presumptive models of how the brain works at higher levels, i.e. at the cortical levels. Examples of such algorithms include Sparsey, Hierarchical Temporal Memory, LSTM and Cogent Confabulation.  We have been designing and building accelerators for these algorithms. We will review these algorithms in some detail. Two versions were designed - a programmable 65 nm SIMD version with Processor in Memory (PiM) extensions and a 65 nm ASIC version. They were compared against a 28 nm GPU baseline using the KTH video action recognition benchmark. Performance/power improvement over the GPU were (Sparsey) SIMD with PiM: 1490; ASIC: 1300; and (HTM) SIMD with PiM: 537; ASIC: 47,100.  Part of the SIMD design is being fabricated as a 3DIC.  Memory bandwidth and capacity is a key bottleneck in many of these algorithms.  Codesigned 3D solutions provide specific advantages.

Short Bio:

Paul D. Franzon is currently the Cirrus Logic Distinguished Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia in 1988.  He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 200 papers in these areas.

11:00W02.4.2Panel: "Can We Jump over the Memory Wall with In-Memory Computing?"
Francky Catthoor1, Ahmed Hemani2, Jean-Francois Roy3, Elisa Vianello4 and Said Hamdioui5
1IMEC, BE; 2Royal Institute of Technology, SE; 3UPMEM, FR; 4CEA-Leti, FR; 5Delft University of Technology, NL

In current conventional computing systems the data is usual transported with a tremendous effort and energy to the computing cores. This has a lot of drawbacks. Thus, near-memory or in-memory computing has evolved as new emerging trend. We will have a spotlight on the advantages and disadvantages of this novel research area.

12:00W02.5Lunch Break
13:00W02.62nd Keynote and Special Session II

Chair:
Bastien Giraud, CEA-Leti, FR, Contact Bastien Giraud

13:00W02.6.1Keynote: Energy-Efficient Processing and Why the Memory Matters
Borivoje Nikolic, UC Berkeley, US

Abstract: New computing applications demand increased system capability, but the end of Moore's Law scaling also means the end of traditional approaches based on scaling conventional general-purpose computing architectures. New architectures and accompanying circuit implementations are required to develop efficient specialized chips for different markets. To provide for ultimate energy efficiency in a broad scope of applications ranging from future mobile clients to warehouse-scale computers (WSCs), the new architectures will optimally utilize a computing substrate based on ultimately scaled CMOS and some of the key emerging device, interconnect and memory technologies. While workloads are constantly changing, the underlying computational primitives are not. The 13 Berkeley computational motifs as the key computational kernels across a wide range of current and emerging applications. By optimally implementing specialized engines for these motifs, including both computation and data movement, optimal energy efficiency can be achieved over a broad range of application domains and underlying technologies.  This talk presents approaches to implementing specialized computing platforms and presents the role of traditional and emerging memory technologies in them.

Bio: Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley.  He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994,  respectively, and the Ph.D. degree from the University of California at Davis in 1999. His research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003.

13:30W02.6.2Pushing the limits: challenges of low-voltage operation in ULL High Density (HD) SRAM
Lorenzo Ciampolini, STMicroelectronics, FR

13:50W02.6.3Evaluation of ternary computing approaches with NVM technologies
Dietmar Fey, FAU, DE

14:10W02.6.4Resistive RAM-Centric Computing: Design and Modeling Methodology
Haitong Li, Stanford University, US

14:30W02.7Coffee Break and Poster Session II

See for the Poster List below.

15:00W02.8Special Session on Emerging RRAMs and MRAMs

Chair:
Said Hamdioui, Delft University of Technology, NL, Contact Said Hamdioui

15:00W02.8.1SOT-MRAM : an energy efficient cache memory alternative
Marc Drouard, Antaios, FR

15:20W02.8.2Majority-based Synthesis for RRAM-based in-memory computing
Pierre-Emmanuel Gaillardon, University of Utah, US

15:40W02.8.3An overview of Normally-off MCU based on hybrid NVM/CMOS circuits
Jean-Michel Portal, IM2NP, FR

16:00W02.9Open Call Paper Session

Chair:
Matthias Jung, University of Kaiserslautern, DE, Contact Matthias Jung

16:00W02.9.1Ultra-Low Power and Compact TFET Multibit Latch and its Applications for Low Voltage Applications
Navneet Gupta, CEA-Leti, FR

16:20W02.9.2MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies
Bruguier Florent, University of Montpellier, FR

16:49W02.10Poster List:
16:49W02.10.1A Non-Volatile Flip-Flop Using Memristive Voltage Divider
Mehrdad Biglari, FAU, DE

16:49W02.10.2In-Memory Computation of Transitive Closure
Alvaro Velasquez, University of Central Florida, US

16:49W02.10.3A Scalable Near-Data Processing Simulator
Geraldo Francisco de Oliveira Junior, Universidade Federal do Rio Grande do Sul, BR

16:49W02.10.4Disruptive 3D Technology: Recent Advances on COOLCUBE(TM)
Mélanie Brocard, CEA-Leti, FR

16:49W02.10.5300 MM & 200 MM ADVANCED MEMORY PLATFORM AND MPW SHUTTLE AT LETI
Elisa Vianello, CEA-Leti, FR

16:49W02.10.64T SRAM Bitcell in 3D CoolCube Technology Exploiting Dynamic Back Biasing
Réda Boumchedda, CEA-Leti, FR

16:50W02.11Closing
16:50W02.11.1Remarks
Christian Weis1 and Bastien Giraud2
1University of Kaiserslautern, DE; 2CEA-Leti, FR