W01 The 5th International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS)

Printer-friendly versionPDF version
Location / Room: 

General Co-Chairs

Jiang Xu, Hong Kong University of Science and Technology, HK (Contact Jiang Xu)
Mahdi Nikdast, Colorado State University, US (Contact Mahdi Nikdast)
Gabriela Nicolescu, Ecole Polytechnique de Montréal, CA (Contact Gabriela Nicolescu)

Programme Committee Chair

Sébastien Le Beux, Lyon Institute of Nanotechnology, FR (Contact Sébastien Le Beux)

Programme Committee Members

Alan Mickelson, University of Colorado Boulder, US (Contact Alan Mickelson)
Ayse Coskun, Boston University, US (Contact Ayse Coskun)
Edoardo Fusella, University of Naples Federico II, IT (Contact Edoardo Fusella)
Nikos Hardavellas, Northwestern University, US (Contact Nikos Hardavellas)
Olivier Sentieys, INRIA, FR (Contact Olivier Sentieys)
Sandro Bartolini, University of Siena, IT (Contact Sandro Bartolini)
Sebastien Rumley, University of Columbia, US (Contact Sebastien Rumley)
Tohru Ishihara, Kyoto University, JP (Contact Tohru Ishihara)
Yaoyao Ye, Shanghai Jiao Tong University, CN (Contact Yaoyao Ye)
Yoan Léger, CNRS – FOTON, FR (Contact Yoan Léger)

Call for Participation and Poster

In Conjunction with Design, Automation & Test in Europe Conference
29th March 2019, Florence, Italy

As Moore's Law is slowing down, an exploration of alternative technologies are developed to replace traditional CMOS-based architectures at the heart of data processing. Moreover, stringent application constraints on massive data transfers in data centers, artificial intelligence systems, and embedded high-performance computing (eHPC), requires new communication-centric systems with novel interconnect technologies. Silicon photonics is a prime candidate to achieve this thanks to its compatibility with CMOS fabrication process, scalability, and growing maturity. OPTICS aims at discussing the most recent advances in silicon photonics for computing systems, covering topics from the device fabrication all the way up to the system-level design through circuit optimization with Electronic-Photonic Design Automation (EPDA). The workshop is of interest to researchers working on silicon photonics, high-performance computing systems and EDA/EPDA. It is comprised of invited talks of the highest caliber from industry and academia addressing most recent outcomes. Ideas and new opportunities are discussed during a panel and a refereed poster presentations session highlights works-in progress.

Topics to be discussed include but are not limited to:

  • EPDA (Electronic-Photonic Design Automation): non-uniformity/thermal aware design, floor-planning, crosstalk-aware interconnects modeling and simulation, etc.
  • Inter/Intra-chip Interconnects: hybrid optical-electronic interconnects, passive/active-based optical switched networks, communication protocols, I/O design etc.
  • Applications: embedded high-performance computing, data center, reservoir computing, all-optical logic gates, etc.
  • Silicon Photonics Devices and Circuits: circuit demonstrator, on-chip lasers, photodetectors, electro-optic modulators, optical switches, athermal devices, etc.

Confirmed speakers:

  • Vladimir Stojanovic, UC Berkeley (US)
  • Bert Offrein, IBM Zurich (CH)
  • Timo Aalto, VTT (Finland)
  • Fabio Pavanello, IMEC (BE)
  • Kholdoun Torki, CMP (FR)
  • Jun Shiomi, Kyoto University (JP)
  • Umar Khan, IMEC (BE)
  • Aditya Narayan, Boston University (US)
  • Cédric Killian, IRISA/INRIA (FR)
  • Yvain Thonnart, CEA-Leti (FR)
  • Davide Bertozzi, University of Ferrara (IT)
  • Laurent Vivien, C2N (FR)
  • Ian O'Connor, ECL (FR)

You are invited to participate and submit your contributions to OPTICS (upto one page). Accepted abstracts will be presented at posters. The submission and notification deadlines are as follows.

Important Dates

Submission deadline: 25th January 2019
Acceptance notification: 30th January 2019

submission website : https://easychair.org/conferences/?conf=optics2019

General Chairs

Jiang Xu, Hong Kong University of Science and Technology
Mahdi Nikdast, Colorado State University
Gabriela Nicolescu, Polytechnique Montréal

Program Chair

Sébastien Le Beux, Lyon Institute of Nanotechnology


07:30W01.1Registration Desk opens
08:30W01.2Workshops start
08:40W01.3From system level simulations to silicon photonic circuit fabrication

08:40 - 09:40 (Keynote) Vladimir Stojanovic, UC Berkeley, US
EPDA for EPSoC design: From co-simulation to photonic circuit generators

09:40 - 10:00 (invited) Kholdoun Torki, CMP, FR
MPW services for Photonics & ICs prototyping

10:00W01.4Coffee break 1
10:30W01.5Silicon Photonics for on-chip interconnects, IO and computing

10:30-10:50 (invited) Timo Aalto, VTT (Finland)
3 µm and 12 µm SOI platforms for optical interconnects and I/O coupling

10:50-11:10 (invited) Fabio Pavanello, IMEC (BE)
Electronics-photonics integration in advanced CMOS platforms using a photonics module: a transceiver application in 65 nm bulk CMOS

11:10-11:30 (invited) Bert Offrein, IBM Zurich (CH)
Advancing silicon photonics for traditional and novel computing paradigms

11:30-11:50 (invited) Jun Shiomi, Kyoto University (JP)
Integrated Optical Neural Networks Exploiting Light Speed Approximate Parallel Multipliers

11:01W01.6Poster Presentation
11:01W01.10Toward large scale on-chip optical interconnects

15:00-15:20 (invited) Umar Khan, IMEC (BE)
Designing large-scale photonic integrated circuits

15:20-15:40 (invited) Ulf Schlichtmann, TUM (DE)
EDA for WRONoCs: From Topology to Physical Design, and Breaking Down Barriers

15:40-16:00 (invited) Aditya Narayan, Boston University (US)
A System-Level Perspective on Silicon Photonic Network-on-Chips

16:00-16:20 (invited) Cédric Killian, IRISA/INRIA (FR)
ONoCs: from offline optimization to run time adaptability

12:00W01.7Lunch break
13:00W01.8Novel Devices for Novel Architectures

13:00-13:20 (invited) Laurent Vivien, C2N (FR)
Recent advances in silicon photonics

13:20-13:40 (invited) Christophe Peucheret, Foton (FR)
Mode division multiplexing for optical networks on chip - potential and limitations

13:40-14:00 (invited) to be defined

14:00-14:20 (invited) Fabrice Raineri or Alfredo De Rossi (FR)

14:30W01.9Coffee break 2
17:30W01.11Workshops end