M03 Emerging Technologies | 3D Integration: Quo Vadis?

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Date: 
2017-03-27
Time: 
0930-13:00
Location / Room: 
3A

Organiser

Partha Pande, Washington State University, US (Contact Partha Pande)

Chair

Krishnendu Chakrabarty, Duke University, US (Contact Krishnendu Chakrabarty)

Download handouts here (Handouts are available for attendees only! The password has been sent to you by email or you may ask for the password at the on-site registration desk.)

Tutorial Plan:

  • 9.30-10.15: Physical Design for 3D ICs (Speaker: Aida-Todri-Sanial, CNRS-LIRMM/University of Montpellier). The topics covered are:

  1. 3D ICs Motivation
  2. 3D IC Design
  3. 3D Power Delivery Network Design
  4. 3D Clock Network Design

  • 10.15-11.00: The Changing Landscape of 3D Memory Architectures (Speaker: Sudeep Pasricha, Colorado State University). The topics covered are:

  1. State-of-the-art in 3D-Stacked Memory Solutions
  2. New Architectures and Directions in 3D-Stacked Memory Design
  3. Communication Interfaces for 3D-Stacked Memory
  4. CAD Tools for 3D-Stacked Memory Design

  • 11.30-12.15: Energy-Efficient and Reliable 3D Network-on-Chip Design (Speaker: Partha Pratim Pande, Washington State University). The topics covered are:

  1. Limitations of Existing 3D NoC Architectures
  2. Incorporating Small-Worldness in 3D NoC
  3. Architecture Optimization
  4. Robustness Against Vertical Link Failures
  5. Performance Evaluation

  • 12.15-13.00: The Hype, Myths, and Realities of Testing 3D ICs (Speaker: Krishnendu Chakrabarty, Duke University). The topics covered are:
  1. Defects and Fault Modeling
  2. Pre-Bond Testing
  3. Post-Bond Testing
  4. Test-flow Selection