M02 OpenCL design flows for Intel and Xilinx FPGAs - common optimization strategies, design patterns and vendor-specific differences

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Date: 
2019-03-25
Time: 
14:00-18:00
Location / Room: 
TBA

Organiser

Tobias Kenter, University of Paderborn, DE (Contact Tobias Kenter)

An increasing fraction of new results in the reconfigurable computing domain are obtained with the help of high level synthesis tools. Among the more popular tools are the OpenCL based Xilinx SDAccel and Intel FPGA SDK for OpenCL. Since they are building upon the same programming model and source language, one would hope for portability between different OpenCL based FPGA designs. However, the vast majority of published research is only optimized for one vendor tool and FPGA family. In their dissemination and training activities, both vendors focus on promoting effective design patterns with their respective tools and for their respective hardware.

In this tutorial, we want to broaden that scope and provide training for both tool chains. During two years of PostDoc research, the workshop organizer has gained extensive experience and insights into these tools. This tutorial will contain step by step optimization examples with performance models based on analysis of generated reports and complemented with measurements and profiling data. We will present design patterns that work well for both tools and thus can promote portability of OpenCL based FPGA designs, but also shed light on differences. Based on examples, we will illustrate the central difference in pipelining of nested loops, which has implications on local memory ports, replication and predictability of design space exploration.

Agenda

TimeLabelSession
13:30M02.1Tutorial and Conference Registration
14:00M02.2Tutorials start
14:00M02.3OpenCL and FPGA design: common constructs and patterns

Speaker:
Tobias Kenter, Paderborn Center for Parallel Computing, DE, Contact Tobias Kenter

14:40M02.4Key differences between Intel FPGA and Xilinx tools: outer loop pipelining, local memory ports and replication

Speaker:
Tobias Kenter, Paderborn Center for Parallel Computing, DE, Contact Tobias Kenter

15:30M02.5Coffee Break for Tutorials
16:00M02.6Simple, yet efficient matrix multiplication designs with OpenCL

Chair:
Tobias Kenter, Paderborn Center for Parallel Computing, DE, Contact Tobias Kenter


  • Design example with Xilinx SDAccel
  • Design example with Intel FPGA SDK for OpenCL
  • Discussion of the used abstraction levels: what do we want the compile to infer, what do we want to express explicitly?
17:10M02.8OpenCL FPGA success stories, complex design examples, libraries

Speaker:
Tobias Kenter, Paderborn Center for Parallel Computing, DE, Contact Tobias Kenter

18:00M02.7Tutorials end
18:00M02.9Welcome Reception & PhD Forum