Physical design is at an inflection point due to growing pains and challenges in SOC/IP design. Need to re-think strategy for design convergence as project durations and # of design iterations to converge the design aren't keeping in check with EDA investments and design methodology innovations
Inflections seen in the last two decades across physical design systems behoove us to re-think our design strategy and TFM innovation in following areas: a) more advancements in floorplan and placement based hierarchical synthesis, b) multi-level hierarchical and intelligent design databases across RTL2GDS, c) hybrid clock planning and implementation structures which provides the best QoR for power and timing targets with least implementation cost, d) raising the abstraction from block level implementation to integrated subsystem planning and convergence, e) SPEC, INTENT and constraints driven SOC/IP Integration framework and f) innovations in mixed-signal design by bringing custom digital design more main-stream. Peeking into the future, in this tutorial we will outline specific suggestions to advance physical design methodologies for continued scale of SOC/IP ecosystem needs. We believe these suggestions (presented in the Tutorial) will help address the semiconductor industry's disruptive transformation from design creation to design convergence and integration.