UB08 Session 8

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Date: Wednesday, March 27, 2019
Time: 16:00 - 18:00
Location / Room:

LabelPresentation Title
Authors
UB08.1RESCUE: EDA TOOLSET FOR INTERDEPENDENT ASPECTS OF RELIABILITY, SECURITY AND QUALITY IN NANOELECTRONIC SYSTEMS DESIGN
Authors:
Cemil Cem Gürsoy1, Guilherme Cardoso Medeiros2, Junchao Chen3, Nevin George4, Josie Esteban Rodriguez Condia5, Thomas Lange6, Aleksa Damljanovic5, Raphael Segabinazzi Ferreira4, Aneesh Balakrishnan6, Xinhui Anna Lai1, Shayesteh Masoumian7, Dmytro Petryk3, Troya Cagil Koylu2, Felipe Augusto da Silva8, Ahmet Cagri Bagbaba8 and Maksim Jenihhin1
1Tallinn University of Technology, EE; 2Delft University of Technology, NL; 3IHP, DE; 4BTU Cottbus-Senftenberg, DE; 5Politecnico di Torino, IT; 6IROC Technologies, FR; 7Intrinsic ID B.V., NL; 8Cadence Design Systems GmbH, DE
Abstract
The demonstrator will introduce an EDA toolset developed by a team of PhD students in the H2020-MSCA-ITN RESCUE project. The recent trends for the computing systems include machine intelligence in the era of IoT, complex safety-critical applications, extreme miniaturization of technologies and intensive interaction with the physical world. These trends set tough requirements on mutually dependent extra-functional design aspects. RESCUE is focused on the key challenges for reliability (functional safety, ageing, soft errors), security (tamper-resistance, PUF technology, intelligent security) and quality (novel fault models, functional test, FMEA/FMECA, verification/debug) and related EDA methodologies. The objective of the interdisciplinary cross-sectoral team from Tallinn UT, TU Delft, BTU Cottbus, POLITO, IHP, IROC, Intrinsic-ID, Cadence and Bosch is to develop in collaboration a holistic EDA toolset for modelling, assessment and enhancement of these extra-functional design aspects.

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UB08.2LOGIC MINIMIZER: LOGIC MINIMIZERS FOR PARTIALLY DEFINED FUNCTIONS
Authors:
Tsutomu Sasao, Kyu Matsuura, Kazuyuki Kai and Yukihiro Iguchi, Meiji University, JP
Abstract
Logic Minimizers for Partially Defined Functions Tsutomu Sasao, Meiji University, Kanagawa 214-0034, Japan. abstract: This demonstration shows a minimization system for partially defined functions. The minimizer reduces the number of the input variables to represent the function using linear transformations. Applications include implementations of random functions; code converter; IP address table; English word list; and URL list. Outline of Demonstration In the demonstration, a PC and a poster are used to show: * Introduction of partially defined functions. * A method to reduce variables by linear decompositions. * Implementation of code converters. * Implementation of IP address tables. * Implementation of English dictionaries. * Implementation of random functions. * Implementation of URL lists.

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UB08.3SWARM: SELF-ORGANIZED WIRING AND ARRANGEMENT OF RESPONSIVE MODULES
Authors:
Daniel Marolt and Jürgen Scheible, Hochschule Reutlingen, DE
Abstract
This demonstration exemplifies a new automation methodology for layout design of analog integrated circuits: Self-organized Wiring and Arrangement of Responsive Modules (SWARM). Based on the idea of decentralization, it addresses the task with an innovative multi-agent system. Its basic principle, similar to the roundup of a sheep herd, is to let responsive layout modules (implemented as procedural generators) interact with each other in a user-defined layout zone. Each module is allowed to autonomously move, rotate and deform itself, while a supervising control organ successively tightens the layout zone to steer the interaction towards increasingly compact layout arrangements. Considering various principles of self-organization, SWARM is able to evoke the phenomenon of emergence: although each module only has a limited viewpoint and selfishly pursues its personal objectives, remarkable overall solutions can emerge on the global scale.

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UB08.4EQ-PYD-NET: ENERGY-EFFICIENT MONOCULAR DEPTH ESTIMATION ON ARM-BASED EMBEDDED PLATFORMS
Authors:
Andrea Calimera1, Valentino Peluso1, Antonio Cipolletta1, Matteo Poggi2, Fabio Tosi2 and Stefano Mattoccia2
1Politecnico di Torino, IT; 2Università di Bologna, IT
Abstract
The demonstration intends to show the implementation of energy-efficient monocular depth estimation using a low-cost CPU for low-power embedded systems. Through the demo we're going to present the PyD-Net depth estimation network, which consists of a lightweight CNN designed for CPUs and able to approach state-of-the-art accuracy. Then we introduce an accuracy-driven complexity reduction strategy based on a hardware-friendly fixed-point quantization. The objective is (i) to demonstrate the portability of the Quantized PyD-Net model into a general-purpose RISC architecture of the ARM Cortex family, (ii) quantify the accuracy-energy tradeoff of unsupervised monocular estimation to establish its use in the embedded domain. During the live demonstration the QPyD-Net will be made running on a Raspberry PI board powered by a Broadcom BCM2837 chip-set.

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UB08.5PREESM: GENERATING ENERGY-OPTIMIZED ADAPTIVE SOFTWARE ON A HETEROGENEOUS PLATFORM WITH PREESM
Authors:
Maxime Pelcat1, Karol Desnos1, Daniel Menard1, Florian Arrestier1, Alexandre Honorat1, Claudio Rubattu2, Antoine Morvan1, Julien Heulot1 and Jean-François Nezan1
1INSA Rennes/IETR, FR; 2UNISS, INSA Rennes/IETR, FR
Abstract
This Booth demonstrates how PREESM and SPIDER tools generate energy-optimized sensor-based adaptive software on a heterogeneous platform. PREESM is a rapid system prototyping tool provided with a runtime manager named SPIDER. PREESM simulates stream processing applications and generates code for multi/many-cores. Processing can either be statically mapped or adaptively managed by SPIDER. Steps when using PREESM are: 1- Model your Application: PREESM provides you with a dataflow language, designed to express parallelism. 2- Model your Architecture: PREESM simulates and generates code for a wide range of systems (e.g., ARM, DSP, FPGA). 3- Prototype and Run your Design: PREESM takes mapping decisions and provides early design space information such as scheduling, memory use, and core loads. PREESM and SPIDER are available on GitHub, and supported by tutorials and a reactive community. PREESM and SPIDER are part of the H2020 CERBERO toolchain. http://preesm.org

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UB08.6ADDRESSING MAN-IN-THE-MIDDLE THREAT IN EXTENSIVELY CONNECTED CARS AND NEXT-GENERATION AUTOMOTIVE NETWORKS
Authors:
Luca Crocetti, Luca Baldanzi and Luca Fanucci, University of Pisa, IT
Abstract
Today's trend in the automotive industry is to integrate more and more interconnected electronics systems in order to offer functionalities and services orientated to the autonomous driving, also by adoption of wireless communication links such as Wi-Fi 802.11p. Thus a connected car results to act as a node of many and heterogeneous networks and thus being exposed to the typical threats of the IT field. The proposed demo aims to investigate the security vulnerabilities of a hypothetical real application scenario exploiting the wireless links and to target the related cybersecurity mechanisms required to counteract possible attacks. The demo consists of two FPGA boards that act as nodes of a 802.11p based network, one as the car and one as an infrastructure unit, and a laptop that acts as malicious entity and performs a Man-In-The-Middle attack. The emulated malicious node alters the communication between the two FPGA nodes and expose the car-like FPGA node to threats as car stealing.

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UB08.7SETA-RAY: A NEW IDE TOOL FOR PREDICTING, ANALYZING AND MITIGATING RADIATION-INDUCED SOFT ERRORS ON FPGAS
Authors:
Luca Sterpone, Boyang Du and Sarah Azimi, Politecnico di Torino, IT
Abstract
One of the main concern for FPGA adopted in mission critical application such as space and avionic fields is radiation-induced soft errors. Therefore, we propose an IDE including two software tools compatible with commercial EDA tools. RAD-RAY as the first and only developed tool capable to predict the source of the SET phenomena by taking in to account the features of the radiation environment such as the type, LET and interaction angle of the particles, the material and physical layout of the device exposed to the radiation. The predicted source SET pulse in provided to the SETA tool as the second developed tool integrated with the commercial FPGA design tool for evaluating the sensitivity of the industrial circuit implemented on Flash-based FPGA and mitigate the original netlist based on the performed analysis. This IDE is supported by ESA and Thales Alenia Space. It has been applied to the EUCLID space mission project that will be launched in 2021.

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UB08.8A MODULAR RECONFIGURABLE DIGITAL MICROFLUIDICS PLATFORM
Authors:
Georgi Tanev1, Winnie Svendsen2 and Jan Madsen3
1Technical University of Denmark, DK; 2DTU Bioengineering, DK; 3DTU Compute, DK
Abstract
Digital microfluidics is a lab-on-a-chip (LOC) technology that allows for manipulation of a small amount of liquids on a chip-scaled device patterned with individually addressable electrodes. Microliter sized droplets can be programmatically dispensed, moved, mixed, react, split and stored thus implementing sample preparation protocols. Combining digital microfluidics with miniaturized analytical methods allows biomedical lab assays to be implemented on a LOC device that provides full sample-to-answer functionality. The growing complexity and integration of the LOC devices impose the need of software tools and hardware instruments to design, simulate, program and operate the broad range of LOC instrumentation needs. To address this matter, we present a modular reconfigurable microfluidics instrumentation platform (shown in Figure 1) capable of evolving to match the instrumentation needs of a specific LOC. The prototype shown in Figure 2 serves the purpose to demonstrate the platform.

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UB08.9MROS AND ZYTLEBOT: DESIGN PLATFORMS FOR EMBEDDED ROBOT SYSTEMS
Authors:
Hideki Takase1, Yasuhiro Nitta1 and So Tamura2
1Kyoto University, JP; 2Kyoto Universiy, JP
Abstract
We are researching design platforms for robot systems based on ROS (Robot Operating System). In the booth, we will present the current status of two research activities. The first project is mROS, a lightweight runtime environment of ROS nodes. mROS offers a ROS-compatible communication library to be operated on the embedded mid-range processor which cannot be operated with Linux. mROS contributes to utilizing low power embedded devices into the ROS system. We will show the case study of mROS on the distributed camera system. The second is ZytleBot, an autonomous driving robot as an FPGA integrated platform utilizing the Xilinx programmable SoC. In ZytleBot, the FPGA performs preprocessing of the road surface image acquired from the camera and calculation of HOG feature calculation for signal detection. We achieved about 5 times faster performance by utilizing the FPGA. We will demonstrate the real-time signal detection task on the ZytleBot that won FPT'18 FPGA design competition.

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UB08.10POETS: PARTIALLY ORDERED EVENT DRIVEN SYSTEMS
Authors:
Jonathan Beaumont1, Ghaith Tarawneh2, Shane Fleming1, Matthew Naylor3, Andrew Brown4, Andrey Mokhov2, Simon Moore3 and David Thomas1
1Imperial College London, GB; 2Newcastle University, GB; 3University of Cambridge, GB; 4University of Southampton, GB
Abstract
POETS technology is based on the idea of an extremely large number of small cores embedded in a fast, hardware, parallel communications infrastructure. The application network communication is effected by small, fixed size hardware data packets (a few bytes). This project is a collaborative effort between 4 UK universities, researching and developing a software methodology and the hardware to realise the potential of this architecture. A POETS booth will consist of live demonstrations of applications benefiting from this architecture, such as Graph Traversal algorithms, Heat Dissipation Equations and Dissipative Particle Dynamics. Applications run on hardware based in Cambridge, and laptops display visualisations of these applications, produced from data output received via wi-fi, allowing visitors to view these applications in real-time. Some of the demonstrations are interactive; a visitor can affect the application and see how this changes the outcome in real-time.

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18:00End of session