UB07 Session 7

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Date: Wednesday, March 27, 2019
Time: 14:00 - 16:00
Location / Room:

LabelPresentation Title
Authors
UB07.1RESCUE: EDA TOOLSET FOR INTERDEPENDENT ASPECTS OF RELIABILITY, SECURITY AND QUALITY IN NANOELECTRONIC SYSTEMS DESIGN
Authors:
Cemil Cem Gürsoy1, Guilherme Cardoso Medeiros2, Junchao Chen3, Nevin George4, Josie Esteban Rodriguez Condia5, Thomas Lange6, Aleksa Damljanovic5, Raphael Segabinazzi Ferreira4, Aneesh Balakrishnan6, Xinhui Anna Lai1, Shayesteh Masoumian7, Dmytro Petryk3, Troya Cagil Koylu2, Felipe Augusto da Silva8, Ahmet Cagri Bagbaba8 and Maksim Jenihhin1
1Tallinn University of Technology, EE; 2Delft University of Technology, NL; 3IHP, DE; 4BTU Cottbus-Senftenberg, DE; 5Politecnico di Torino, IT; 6IROC Technologies, FR; 7Intrinsic ID B.V., NL; 8Cadence Design Systems GmbH, DE
Abstract
The demonstrator will introduce an EDA toolset developed by a team of PhD students in the H2020-MSCA-ITN RESCUE project. The recent trends for the computing systems include machine intelligence in the era of IoT, complex safety-critical applications, extreme miniaturization of technologies and intensive interaction with the physical world. These trends set tough requirements on mutually dependent extra-functional design aspects. RESCUE is focused on the key challenges for reliability (functional safety, ageing, soft errors), security (tamper-resistance, PUF technology, intelligent security) and quality (novel fault models, functional test, FMEA/FMECA, verification/debug) and related EDA methodologies. The objective of the interdisciplinary cross-sectoral team from Tallinn UT, TU Delft, BTU Cottbus, POLITO, IHP, IROC, Intrinsic-ID, Cadence and Bosch is to develop in collaboration a holistic EDA toolset for modelling, assessment and enhancement of these extra-functional design aspects.

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UB07.2EDP PLAYER: A DESIGN ASSISTANT FOR PROCEDURAL DESIGN AUTOMATION OF ANALOG INTEGRATED CIRCUITS
Authors:
Matthias Schweikardt1, Husni Habal2 and Jürgen Scheible1
1Hochschule Reutlingen, DE; 2Infineon Technologies, DE
Abstract
In this demonstration, we address procedural circuit design automation of analog integrated circuits. Procedural automation means, that the knowledge-based strategy of human experts is captured in an executable script, which makes it reusable. We call this principle EDP (Expert Design Plan). An EDP can cover different performance parameters, technologies and topologies. We present the EDP Player, which enables the creation and execution of plain EDPs. The tool provides a preliminary version of an instruction set tailored to the typical manual analog circuit design flow, called EDPL (EDP-Language). The tool is fully integrated within Cadence Virtuoso based on Cadence SKILL. The tool has been utilized for three different examples: the automated design of a miller operational amplifier, a bandgap, and the automated creation of variants of a smart power IC. The usage of EDPs leads to a strong reduction of design time without loss of both design quality and reliability.

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UB07.3A FAST PROTOTYPING FRAMEWORK FOR SERVICE-ORIENTED AUTOMOTIVE APPLICATIONS
Authors:
Matthias Becker, Zhonghai Lu and De-Jiu Chen, KTH Royal Institute of Technology, SE
Abstract
Service-Oriented Architectures (SOA) provide a flexible platform for advanced automotive software applications. We present a research platform for fast prototyping of platform software and applications. The hardware is built around a RC car. Several sensors and actuators are connected over microcontrollers that can be accessed from higher-level ECUs over bus connections. User applications are executed on 4 Linux-based ECUs which communicate over a multi-hop Ethernet network. All communication of applications is realized over SOME-IP, an automotive middleware layer that is based on the SOA principle. The development framework generates code skeletons for user tasks, and all required management and configuration code of the underlying SOA framework, based on a user specified application model. It is then automatically transferred and compiled on the respective ECUs. We show the usability of the platform by a remote-operation scenario.

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UB07.4EQ-PYD-NET: ENERGY-EFFICIENT MONOCULAR DEPTH ESTIMATION ON ARM-BASED EMBEDDED PLATFORMS
Authors:
Andrea Calimera1, Valentino Peluso1, Antonio Cipolletta1, Matteo Poggi2, Fabio Tosi2 and Stefano Mattoccia2
1Politecnico di Torino, IT; 2Università di Bologna, IT
Abstract
The demonstration intends to show the implementation of energy-efficient monocular depth estimation using a low-cost CPU for low-power embedded systems. Through the demo we're going to present the PyD-Net depth estimation network, which consists of a lightweight CNN designed for CPUs and able to approach state-of-the-art accuracy. Then we introduce an accuracy-driven complexity reduction strategy based on a hardware-friendly fixed-point quantization. The objective is (i) to demonstrate the portability of the Quantized PyD-Net model into a general-purpose RISC architecture of the ARM Cortex family, (ii) quantify the accuracy-energy tradeoff of unsupervised monocular estimation to establish its use in the embedded domain. During the live demonstration the QPyD-Net will be made running on a Raspberry PI board powered by a Broadcom BCM2837 chip-set.

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UB07.5T-CREST: THE TIME-PREDICTABLE MULTICORE PROCESSOR T-CREST
Authors:
Martin Schöberl, Luca Pezzarossa and Jens Sparso, Technical University of Denmark, DK
Abstract
Future real-time systems, such as advanced control systems or real-time image recognition, need more powerful processors, but still a system where the worst-case execution time (WCET) can be statically predicted. Multicore processors are one answer to the need for more processing power. However, it is still an open research question how to best organize and implement time-predictable communication between processing cores. T-CREST is an open-source multicore processor for research on time-predictable computer architecture. In consists of several Patmos processors connected by various time-predictable communication structures: access to shared off-chip, access to shared on-chip memory, and the Argo network-on-chip for fast inter-processor communication. T-CREST is supported by open-source development tools, such as compilation and WCET analysis. To best of our knowledge, T-CREST is the only fully open-source architecture for research on future real-time multicore architectures.

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UB07.6ADDRESSING MAN-IN-THE-MIDDLE THREAT IN EXTENSIVELY CONNECTED CARS AND NEXT-GENERATION AUTOMOTIVE NETWORKS
Authors:
Luca Crocetti, Luca Baldanzi and Luca Fanucci, University of Pisa, IT
Abstract
Today's trend in the automotive industry is to integrate more and more interconnected electronics systems in order to offer functionalities and services orientated to the autonomous driving, also by adoption of wireless communication links such as Wi-Fi 802.11p. Thus a connected car results to act as a node of many and heterogeneous networks and thus being exposed to the typical threats of the IT field. The proposed demo aims to investigate the security vulnerabilities of a hypothetical real application scenario exploiting the wireless links and to target the related cybersecurity mechanisms required to counteract possible attacks. The demo consists of two FPGA boards that act as nodes of a 802.11p based network, one as the car and one as an infrastructure unit, and a laptop that acts as malicious entity and performs a Man-In-The-Middle attack. The emulated malicious node alters the communication between the two FPGA nodes and expose the car-like FPGA node to threats as car stealing.

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UB07.7ASAM: AUTOMATIC SYNTHESIS OF ALGORITHMS ON MULTI CHIP/FPGA WITH COMMUNICATION CONSTRAINTS
Authors:
Amir Masoud Gharehbaghi, Tomohiro Maruoka, Yukio Miyasaka, Akihiro Goda, Amir Masoud Gharehbaghi and Masahiro Fujita, The University of Tokyo, JP
Abstract
Mapping of large systems/computations on multiple chips/multiple cores needs sophisticated compilation methods. In this demonstration, we present our compiler tools for multi-chip and multi-core systems that considers communication architecture and the related constraints for optimal mapping. Specifically, we demonstrate compilation methods for multi-chip connected with ring topology, and multi-core connected with mesh topology, assuming fine-grained reconfigurable cores, as well as generalization techniques for large problems size as convolutional neural networks. We will demonstrate our mappings methods starting from data-flow graphs (DFGs) and equations, specifically with applications to convolutional neural networks (CNNs) for convolution layers as well as fully connected layers.

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UB07.8MECO: AN AUTONOMIC MANAGER FOR EDGE-COMPUTING PLATFORMS
Authors:
Gabriella D'Andrea, Tania Di Mascio, Luigi Pomante and Giacomo Valente, University of L'Aquila, IT
Abstract
In the Cyber-Physical-Systems word, the need for hardware platforms able to satisfy increasing requirements in computing performance, while keeping the adaptability imposed by the interactions with the physical world is leading on the use FPGAs, due to their inherent run-time reconfigurability. So, this demo presents an implementation of a self-adaptive loop for edge- computing devices targeting FPGAs. An adaptive run-time manager, together with a smart monitoring system, evaluates the quality of service and determines whether is convenient to perform a dynamic partial reconfiguration. The whole development flow, that exploits a library of elements to compose the monitoring system and then selects the appropriate manager, will be shown by means of a reference use case implemented on a Zynq Ultrascale+ SoC. Finally, a comparison among different functionalities will be illustrated as well.

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UB07.9LABSMILING: A SAAS FRAMEWORK, COMPOSED OF A NUMBER OF REMOTELY ACCESSIBLE TESTBEDS AND RELATED SW TOOLS, FOR ANALYSIS, DESIGN AND MANAGEMENT OF LOW DATA-RATE WIRELESS PERSONAL AREA NETWORKS BASED ON IEEE 802.15.4
Authors:
Carlo Centofanti, Luigi Pomante, Marco Santic and Walter Tiberti, University of L'Aquila, IT
Abstract
Low data-rate wireless personal area networks (LR-WPANs) are constantly increasing their presence in the fields of IoT, wearable, home automation, health monitoring. The development, deployment and testing of SW based on IEEE 802.15.4 standard (and derivations, e.g. 15.4e), require the exploitation of a testbed as the network grows in complexity and heterogeneity. This demo shows LabSmiling: a SaaS framework which connects testbeds deployed in a real-world-environment and the related SW tools that make available a meaningful (but still scalable) number of physical devices (sensor nodes) to developers. It provides a comfortable out-of-the-box service designed to fulfill developer needs giving them full control on single motes (program, reset, physical power on/off, up/down links, commands/messages/packets in/from the network). Advanced services are: full-customizable testing scenario, validation/testing protocol compliances/extensions, run low level packet sniffers with QoS metrics.

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UB07.10REQV: A TOOL FOR REQUIREMENTS FORMAL CONSISTENCY CHECKING
Authors:
Luca Pulina1, Massimo Narizzano2, Armando Tacchella2 and Simone Vuotto1
1University of Sassari, IT; 2University of Genoa, IT
Abstract
In the demo we will present ReqV, a tool for requirements formal consistency checking developed in the context of the H2020 EU project CERBERO (http://www.cerbero-h2020.eu/tools-and-tutorials/). ReqV takes as input a set of requirements expressed in natural language, so it does not require any background knowledge of formal methods and logical languages. A video tutorial is currently available at http://www.cluster-prossimo.it/docs/ReqV_video.mp4. The basic technologies used in ReqV are an extension of Property Specification Patterns to constrained numerical signals -- which enables to write useful requirements specifications in the context of Cyber-Physical Systems -- and Linear Temporal Logic satisfiability solvers for the formal consistency checking part. In the case of inconsistency of the set of input requirements, ReqV can also extract the minimal set of conflicting requirements, in order to help the designer to correct a wrong specification.

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16:00End of session